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git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-22 09:11:26 +03:00
nvadsp: Move DRAM map to custom property
Move DRAM map DT entries from 'reg' to a new custom property "nvidia,dram_map". This is to restrict the use of 'reg' only for actual registers, which will be tightly controlled by 'ranges' property. Bug 4164138 Bug 3682950 Change-Id: Ia535d136b15a0ba6d7758ed3a2d70ace2c8cf763 Signed-off-by: Viswanath L <viswanathl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2983549 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -280,6 +280,21 @@ static int __init nvadsp_parse_dt(struct platform_device *pdev)
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}
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}
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}
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}
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for (iter = 0; iter < MAX_DRAM_MAP; iter++) {
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if (of_property_read_u64_index(dev->of_node,
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"nvidia,dram_map", (iter * MAX_DRAM_MAP),
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&drv_data->dram_map[iter].addr))
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break;
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if (of_property_read_u64_index(dev->of_node,
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"nvidia,dram_map", (iter * MAX_DRAM_MAP) + 1,
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&drv_data->dram_map[iter].size)) {
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dev_err(dev,
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"Failed to get DRAM map with ID %d\n", iter);
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return -EINVAL;
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}
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}
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if (!of_property_read_string(dev->of_node,
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if (!of_property_read_string(dev->of_node,
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"nvidia,adsp_elf", &adsp_elf)) {
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"nvidia,adsp_elf", &adsp_elf)) {
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if (strlen(adsp_elf) < MAX_FW_STR)
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if (strlen(adsp_elf) < MAX_FW_STR)
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@@ -334,7 +349,7 @@ static int __init nvadsp_probe(struct platform_device *pdev)
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void __iomem *base = NULL;
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void __iomem *base = NULL;
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uint32_t aram_addr;
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uint32_t aram_addr;
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uint32_t aram_size;
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uint32_t aram_size;
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int dram_iter, irq_iter, iter;
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int irq_iter, iter;
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int irq_num;
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int irq_num;
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int ret = 0;
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int ret = 0;
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@@ -403,18 +418,6 @@ static int __init nvadsp_probe(struct platform_device *pdev)
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drv_data->base_regs_saved = drv_data->base_regs;
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drv_data->base_regs_saved = drv_data->base_regs;
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for (dram_iter = 0; dram_iter < ADSP_MAX_DRAM_MAP; dram_iter++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, iter++);
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if (!res) {
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dev_err(dev,
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"Failed to get DRAM map with ID %d\n", iter);
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ret = -EINVAL;
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goto out;
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}
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drv_data->dram_region[dram_iter] = res;
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}
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for (irq_iter = 0; irq_iter < NVADSP_VIRQ_MAX; irq_iter++) {
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for (irq_iter = 0; irq_iter < NVADSP_VIRQ_MAX; irq_iter++) {
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irq_num = platform_get_irq(pdev, irq_iter);
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irq_num = platform_get_irq(pdev, irq_iter);
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if (irq_num < 0) {
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if (irq_num < 0) {
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@@ -32,12 +32,6 @@ enum {
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APE_MAX_REG
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APE_MAX_REG
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};
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};
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enum {
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ADSP_DRAM1,
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ADSP_DRAM2,
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ADSP_MAX_DRAM_MAP
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};
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/*
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/*
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* Note: These enums should be aligned to the adsp_mem node mentioned in the
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* Note: These enums should be aligned to the adsp_mem node mentioned in the
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* device tree
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* device tree
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@@ -82,6 +76,14 @@ enum adsp_evp_dt {
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#define NVADSP_ELF "adsp.elf"
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#define NVADSP_ELF "adsp.elf"
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#define MAX_FW_STR 30
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#define MAX_FW_STR 30
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/* Max no. of entries in "nvidia,cluster_mem" */
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#define MAX_DRAM_MAP 2
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struct nvadsp_reg_map {
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u64 addr;
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u64 size;
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};
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enum nvadsp_virqs {
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enum nvadsp_virqs {
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MBOX_SEND_VIRQ,
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MBOX_SEND_VIRQ,
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MBOX_RECV_VIRQ,
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MBOX_RECV_VIRQ,
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@@ -157,7 +159,6 @@ struct nvadsp_drv_data {
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void __iomem **base_regs;
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void __iomem **base_regs;
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void __iomem **base_regs_saved;
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void __iomem **base_regs_saved;
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struct platform_device *pdev;
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struct platform_device *pdev;
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struct resource *dram_region[ADSP_MAX_DRAM_MAP];
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struct hwmbox_queue hwmbox_send_queue;
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struct hwmbox_queue hwmbox_send_queue;
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struct nvadsp_mbox **mboxes;
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struct nvadsp_mbox **mboxes;
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@@ -245,6 +246,9 @@ struct nvadsp_drv_data {
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/* "nvidia,cluster_mem" */
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/* "nvidia,cluster_mem" */
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struct nvadsp_cluster_mem cluster_mem[MAX_CLUSTER_MEM];
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struct nvadsp_cluster_mem cluster_mem[MAX_CLUSTER_MEM];
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/* "nvidia,dram_map" */
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struct nvadsp_reg_map dram_map[MAX_DRAM_MAP];
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};
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};
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#define ADSP_CONFIG 0x04
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#define ADSP_CONFIG 0x04
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@@ -93,7 +93,6 @@ struct nvadsp_os_data {
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struct platform_device *pdev;
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struct platform_device *pdev;
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struct global_sym_info *adsp_glo_sym_tbl;
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struct global_sym_info *adsp_glo_sym_tbl;
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void __iomem *hwmailbox_base;
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void __iomem *hwmailbox_base;
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struct resource **dram_region;
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struct nvadsp_debug_log logger;
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struct nvadsp_debug_log logger;
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struct nvadsp_cnsl console;
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struct nvadsp_cnsl console;
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struct work_struct restart_os_work;
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struct work_struct restart_os_work;
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@@ -303,13 +302,19 @@ err_out:
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bool is_adsp_dram_addr(u64 addr)
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bool is_adsp_dram_addr(u64 addr)
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{
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{
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int i;
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int i;
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struct resource **dram = priv.dram_region;
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struct nvadsp_drv_data *drv_data = platform_get_drvdata(priv.pdev);
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for (i = 0; i < ADSP_MAX_DRAM_MAP; i++) {
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for (i = 0; i < MAX_DRAM_MAP; i++) {
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if ((dram[i]->start) && (addr >= dram[i]->start) &&
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struct nvadsp_reg_map *dram = &drv_data->dram_map[i];
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(addr <= dram[i]->end))
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if (dram->size == 0)
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break;
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if ((addr >= dram->addr) &&
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(addr < (dram->addr + dram->size)))
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return true;
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return true;
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}
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}
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return false;
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return false;
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}
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}
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@@ -2596,7 +2601,6 @@ int __init nvadsp_os_probe(struct platform_device *pdev)
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int ret = 0;
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int ret = 0;
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priv.hwmailbox_base = drv_data->base_regs[hwmb_reg_idx()];
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priv.hwmailbox_base = drv_data->base_regs[hwmb_reg_idx()];
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priv.dram_region = drv_data->dram_region;
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priv.adsp_os_addr = drv_data->adsp_mem[ADSP_OS_ADDR];
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priv.adsp_os_addr = drv_data->adsp_mem[ADSP_OS_ADDR];
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priv.adsp_os_size = drv_data->adsp_mem[ADSP_OS_SIZE];
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priv.adsp_os_size = drv_data->adsp_mem[ADSP_OS_SIZE];
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