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nvadsp: Move DRAM map to custom property

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Move DRAM map DT entries from 'reg' to a new custom
property "nvidia,dram_map". This is to restrict the
use of 'reg' only for actual registers, which will
be tightly controlled by 'ranges' property.

Bug 4164138
Bug 3682950

Change-Id: Ia535d136b15a0ba6d7758ed3a2d70ace2c8cf763
Signed-off-by: Viswanath L <viswanathl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2983549
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Viswanath L
2023-09-22 03:15:27 +00:00
committed by mobile promotions
parent fa4a7643c5
commit e45c6bc8a9
3 changed files with 37 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/platform/tegra/nvadsp/dev.c
View File

@@ -280,6 +280,21 @@ static int __init nvadsp_parse_dt(struct platform_device *pdev)
}
}
for (iter = 0; iter < MAX_DRAM_MAP; iter++) {
if (of_property_read_u64_index(dev->of_node,
"nvidia,dram_map", (iter * MAX_DRAM_MAP),
&drv_data->dram_map[iter].addr))
break;
if (of_property_read_u64_index(dev->of_node,
"nvidia,dram_map", (iter * MAX_DRAM_MAP) + 1,
&drv_data->dram_map[iter].size)) {
dev_err(dev,
"Failed to get DRAM map with ID %d\n", iter);
return -EINVAL;
}
}
if (!of_property_read_string(dev->of_node,
"nvidia,adsp_elf", &adsp_elf)) {
if (strlen(adsp_elf) < MAX_FW_STR)
@@ -334,7 +349,7 @@ static int __init nvadsp_probe(struct platform_device *pdev)
void __iomem *base = NULL;
uint32_t aram_addr;
uint32_t aram_size;
int dram_iter, irq_iter, iter;
int irq_iter, iter;
int irq_num;
int ret = 0;
@@ -403,18 +418,6 @@ static int __init nvadsp_probe(struct platform_device *pdev)
drv_data->base_regs_saved = drv_data->base_regs;
for (dram_iter = 0; dram_iter < ADSP_MAX_DRAM_MAP; dram_iter++) {
res = platform_get_resource(pdev, IORESOURCE_MEM, iter++);
if (!res) {
dev_err(dev,
"Failed to get DRAM map with ID %d\n", iter);
ret = -EINVAL;
goto out;
}
drv_data->dram_region[dram_iter] = res;
}
for (irq_iter = 0; irq_iter < NVADSP_VIRQ_MAX; irq_iter++) {
irq_num = platform_get_irq(pdev, irq_iter);
if (irq_num < 0) {

18
drivers/platform/tegra/nvadsp/dev.h
View File

@@ -32,12 +32,6 @@ enum {
APE_MAX_REG
};
enum {
ADSP_DRAM1,
ADSP_DRAM2,
ADSP_MAX_DRAM_MAP
};
/*
* Note: These enums should be aligned to the adsp_mem node mentioned in the
* device tree
@@ -82,6 +76,14 @@ enum adsp_evp_dt {
#define NVADSP_ELF "adsp.elf"
#define MAX_FW_STR 30
/* Max no. of entries in "nvidia,cluster_mem" */
#define MAX_DRAM_MAP 2
struct nvadsp_reg_map {
u64 addr;
u64 size;
};
enum nvadsp_virqs {
MBOX_SEND_VIRQ,
MBOX_RECV_VIRQ,
@@ -157,7 +159,6 @@ struct nvadsp_drv_data {
void __iomem **base_regs;
void __iomem **base_regs_saved;
struct platform_device *pdev;
struct resource *dram_region[ADSP_MAX_DRAM_MAP];
struct hwmbox_queue hwmbox_send_queue;
struct nvadsp_mbox **mboxes;
@@ -245,6 +246,9 @@ struct nvadsp_drv_data {
/* "nvidia,cluster_mem" */
struct nvadsp_cluster_mem cluster_mem[MAX_CLUSTER_MEM];
/* "nvidia,dram_map" */
struct nvadsp_reg_map dram_map[MAX_DRAM_MAP];
};
#define ADSP_CONFIG 0x04

16
drivers/platform/tegra/nvadsp/os.c
View File

@@ -93,7 +93,6 @@ struct nvadsp_os_data {
struct platform_device *pdev;
struct global_sym_info *adsp_glo_sym_tbl;
void __iomem *hwmailbox_base;
struct resource **dram_region;
struct nvadsp_debug_log logger;
struct nvadsp_cnsl console;
struct work_struct restart_os_work;
@@ -303,13 +302,19 @@ err_out:
bool is_adsp_dram_addr(u64 addr)
{
int i;
struct resource **dram = priv.dram_region;
struct nvadsp_drv_data *drv_data = platform_get_drvdata(priv.pdev);
for (i = 0; i < ADSP_MAX_DRAM_MAP; i++) {
if ((dram[i]->start) && (addr >= dram[i]->start) &&
(addr <= dram[i]->end))
for (i = 0; i < MAX_DRAM_MAP; i++) {
struct nvadsp_reg_map *dram = &drv_data->dram_map[i];
if (dram->size == 0)
break;
if ((addr >= dram->addr) &&
(addr < (dram->addr + dram->size)))
return true;
}
return false;
}
@@ -2596,7 +2601,6 @@ int __init nvadsp_os_probe(struct platform_device *pdev)
int ret = 0;
priv.hwmailbox_base = drv_data->base_regs[hwmb_reg_idx()];
priv.dram_region = drv_data->dram_region;
priv.adsp_os_addr = drv_data->adsp_mem[ADSP_OS_ADDR];
priv.adsp_os_size = drv_data->adsp_mem[ADSP_OS_SIZE];