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vi5_fops: fix mem leak

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release capture requests and embedded data
buffers before closing and exiting the stream

bug 4336756

Change-Id: Iba856eea9757a8226bc949ae1d72a87adf2d55eb
Signed-off-by: Anubhav rai <arai@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3068424
Reviewed-by: Praveen AC <pac@nvidia.com>
Reviewed-by: Jerry Chang <jerchang@nvidia.com>
Reviewed-by: Ankur Pawar <ankurp@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Anubhav rai
2024-02-02 01:40:35 +00:00
committed by mobile promotions
parent bec1d86778
commit e5075835ab
2 changed files with 25 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/media/platform/tegra/camera/vi/vi5_fops.c
View File

@@ -2,7 +2,7 @@
/* /*
* Tegra Video Input 5 device common APIs * Tegra Video Input 5 device common APIs
* *
* Copyright (c) 2016-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * Copyright (c) 2016-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*/ */
#include <linux/errno.h> #include <linux/errno.h>
@@ -319,6 +319,8 @@ static int tegra_channel_capture_setup(struct tegra_channel *chan, unsigned int
chan->request[vi_port] = dma_alloc_coherent(chan->tegra_vi_channel[vi_port]->rtcpu_dev, chan->request[vi_port] = dma_alloc_coherent(chan->tegra_vi_channel[vi_port]->rtcpu_dev,
setup.queue_depth * setup.request_size, setup.queue_depth * setup.request_size,
&setup.iova, GFP_KERNEL); &setup.iova, GFP_KERNEL);
chan->request_iova[vi_port] = setup.iova;
if (chan->request[vi_port] == NULL) { if (chan->request[vi_port] == NULL) {
dev_err(chan->vi->dev, "dma_alloc_coherent failed\n"); dev_err(chan->vi->dev, "dma_alloc_coherent failed\n");
return -ENOMEM; return -ENOMEM;
@@ -967,6 +969,24 @@ static int vi5_channel_stop_streaming(struct vb2_queue *vq)
dev_err(&chan->video->dev, dev_err(&chan->video->dev,
"vi capture release failed\n"); "vi capture release failed\n");
/* Release capture requests */
if (chan->request[vi_port] != NULL) {
dma_free_coherent(chan->tegra_vi_channel[vi_port]->rtcpu_dev,
chan->capture_queue_depth * sizeof(struct capture_descriptor),
chan->request[vi_port], chan->request_iova[vi_port]);
}
chan->request[vi_port] = NULL;
/* Release emd data buffers */
if (chan->emb_buf_size > 0) {
struct device *vi_unit_dev;
vi5_unit_get_device_handle(chan->vi->ndev, chan->port[0],\
&vi_unit_dev);
dma_free_coherent(vi_unit_dev, chan->emb_buf_size,
chan->emb_buf_addr, chan->emb_buf);
chan->emb_buf_size = 0;
}
vi_channel_close_ex(chan->vi_channel_id[vi_port], vi_channel_close_ex(chan->vi_channel_id[vi_port],
chan->tegra_vi_channel[vi_port]); chan->tegra_vi_channel[vi_port]);
chan->tegra_vi_channel[vi_port] = NULL; chan->tegra_vi_channel[vi_port] = NULL;
@@ -974,6 +994,7 @@ static int vi5_channel_stop_streaming(struct vb2_queue *vq)
/* release all remaining buffers to v4l2 */ /* release all remaining buffers to v4l2 */
tegra_channel_queued_buf_done(chan, VB2_BUF_STATE_ERROR, false); tegra_channel_queued_buf_done(chan, VB2_BUF_STATE_ERROR, false);
} }
return 0; return 0;

4
include/media/mc_common.h
View File

@@ -2,7 +2,7 @@
/* /*
* Tegra Media controller common APIs * Tegra Media controller common APIs
* *
* Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * Copyright (c) 2012-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*/ */
#ifndef __CAMERA_MC_COMMON_H__ #ifndef __CAMERA_MC_COMMON_H__
@@ -251,6 +251,8 @@ struct tegra_channel {
struct nvcsi_deskew_context *deskew_ctx; struct nvcsi_deskew_context *deskew_ctx;
struct tegra_vi_channel *tegra_vi_channel[TEGRA_CSI_BLOCKS]; struct tegra_vi_channel *tegra_vi_channel[TEGRA_CSI_BLOCKS];
struct capture_descriptor *request[TEGRA_CSI_BLOCKS]; struct capture_descriptor *request[TEGRA_CSI_BLOCKS];
dma_addr_t request_iova[TEGRA_CSI_BLOCKS];
bool is_slvsec; bool is_slvsec;
int is_interlaced; int is_interlaced;
enum interlaced_type interlace_type; enum interlaced_type interlace_type;