From e66ce07df10789a262bce32cfce0ddebdb8b4972 Mon Sep 17 00:00:00 2001 From: Dipesh Gandhi Date: Mon, 10 Oct 2016 11:02:51 +0530 Subject: [PATCH] ASoC: asrc: clear asrc interrupt twice As per HW Bug 200208400 we need to clear asrc interrupt twice to update interrupt status register. Bug 200219757 Change-Id: I741f27cca155e45f0112f505eed415852f13e219 Signed-off-by: Dipesh Gandhi Reviewed-on: http://git-master/r/1233840 Reviewed-by: Mohan Kumar D GVS: Gerrit_Virtual_Submit Reviewed-by: Nitin Pai --- sound/soc/tegra-alt/tegra186_asrc_alt.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/sound/soc/tegra-alt/tegra186_asrc_alt.c b/sound/soc/tegra-alt/tegra186_asrc_alt.c index 450fc6a9..5630d80b 100644 --- a/sound/soc/tegra-alt/tegra186_asrc_alt.c +++ b/sound/soc/tegra-alt/tegra186_asrc_alt.c @@ -201,6 +201,11 @@ static int tegra186_asrc_runtime_resume(struct device *dev) regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_INT_CLEAR, 0x01); +#if defined(CONFIG_TEGRA186_ASRC_INT_CLEAR_WAR) + /* Hw Bug:200208400 - asrc interrupt status gets cleared when + it is cleared twice */ + regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_INT_CLEAR, 0x1); +#endif for (lane_id = 0; lane_id < 6; lane_id++) { if (asrc->lane[lane_id].ratio_source == RATIO_SW) { regmap_write(asrc->regmap, @@ -1078,6 +1083,11 @@ static void tegra186_asrc_ahc_cb(void *data) regcache_cache_bypass(asrc->regmap, true); regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_INT_CLEAR, 0x1); +#if defined(CONFIG_TEGRA186_ASRC_INT_CLEAR_WAR) + /* Hw Bug:200208400 - asrc interrupt status gets cleared when + it is cleared twice */ + regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_INT_CLEAR, 0x1); +#endif regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, 0x0); udelay(100); regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, 0x1);