From e69d77ec7137d0e3353da45c3b08cb8ed4ac2fef Mon Sep 17 00:00:00 2001 From: Mika Liljeberg Date: Fri, 22 Apr 2022 13:38:12 +0300 Subject: [PATCH] firmware-api: add commands for I2C over HSP Add command specifications for RCE I2C HSP protocol. Jira CAMERASW-1404 Change-Id: I17cbe234371140934b04e3a9683aa1cbc7d5ef91 Signed-off-by: Mika Liljeberg Reviewed-on: https://git-master.nvidia.com/r/c/tegra/camera/firmware-api/+/2701487 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2988962 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2988975 GVS: Gerrit_Virtual_Submit Reviewed-by: Matti Ryttylainen Reviewed-by: Viktor Horsmanheimo --- include/soc/tegra/camrtc-commands.h | 69 +++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/include/soc/tegra/camrtc-commands.h b/include/soc/tegra/camrtc-commands.h index f6121256..53583349 100644 --- a/include/soc/tegra/camrtc-commands.h +++ b/include/soc/tegra/camrtc-commands.h @@ -34,6 +34,35 @@ */ #define CAMRTC_HSP_IRQ MK_U32(0x00) +/** + * Configure I2C controller. This will activate the given + * I2C controller and configure the base address of a shared memory + * buffer for subsequent I2C transfers. Buffer must be page aligned. + * + * param[23:20] = I2C bus ID + * param[19:0] = Bits [31:12] of shared memory buffer bus address + */ +#define CAMRTC_HSP_I2C_INIT MK_U32(0x10) + +/** + * Configure I2C device address. This will set the slave device + * for subsequent I2C transfers. + * + * param[23:20] = I2C bus ID + * param[10:10] = 10-bit address flag + * param[9:0] = device address + */ +#define CAMRTC_HSP_I2C_DEVICE MK_U32(0x11) + +/** + * Perform I2C transfer. The same shared memory buffer will be used + * for send and receive. Either byte count may be set to zero. + * + * param[23:12] = recv byte count + * param[11:0] = send byte count + */ +#define CAMRTC_HSP_I2C_XFER MK_U32(0x12) + /** * The HELLO messages are exchanged at the beginning of VM and RCE FW session. * The HELLO message exchange ensures there are no unprocessed messages @@ -123,6 +152,36 @@ * between Camera VM and RCE FW. */ #define RTCPU_CMD_CH_SETUP MK_U32(6) + +/** + * Configure I2C controller. This will activate the given + * I2C controller and configure the base address of a shared memory + * buffer for subsequent I2C transfers. Buffer must be page aligned. + * + * param[23:20] = I2C bus ID + * param[19:0] = Bits [31:12] of shared memory buffer bus address + */ +#define RTCPU_CMD_I2C_INIT MK_U32(0x10) + +/** + * Configure I2C device address. This will set the slave device + * for subsequent I2C transfers. + * + * param[23:20] = I2C bus ID + * param[10:10] = 10-bit address flag + * param[9:0] = device address + */ +#define RTCPU_CMD_I2C_DEVICE MK_U32(0x11) + +/** + * Perform I2C transfer. The same shared memory buffer will be used + * for send and receive. Either byte count may be set to zero. + * + * param[23:12] = recv byte count + * param[11:0] = send byte count + */ +#define RTCPU_CMD_I2C_XFER MK_U32(0x12) + #define RTCPU_CMD_RESERVED_5E MK_U32(0x5E) /* bug 200395605 */ #define RTCPU_CMD_RESERVED_7D MK_U32(0x7d) #define RTCPU_CMD_RESERVED_7E MK_U32(0x7e) @@ -162,4 +221,14 @@ /** @} */ +/** + * @defgroup I2C HSP protocol responses + * @{ + */ +#define RTCPU_I2C_DONE MK_U32(1) +#define RTCPU_I2C_ERROR MK_U32(2) +#define RTCPU_I2C_NACK MK_U32(3) +#define RTCPU_I2C_ARBL MK_U32(4) +/** @} */ + #endif /* INCLUDE_CAMRTC_COMMANDS_H */