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PCI: tegra264: Disable RST# IRQ when EP not ready
Enabled RST# IRQ during EP_START after tegra264_pcie_ep_rst_deassert is invoked for EP and disable RST# IRQ during EP_STOP after tegra264_pcie_ep_rst_assert is executed for EP and EP is not available anymore. This prevents unwanted EP accesses during RP reset sequence causing PERST# to toggle, while EP is not ready or available. Bug 5281037 Change-Id: I43e1fd6c6ccfaae64a6bb2375a3685f186766d78 Signed-off-by: Prakhar Srivastava <prasrivastav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3363313 Reviewed-by: svcacv <svcacv@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
This commit is contained in:
committed by
Jon Hunter
parent
9c6469ff98
commit
e6a11f7e4c
@@ -545,12 +545,15 @@ static int tegra264_pcie_ep_start(struct pci_epc *epc)
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gpiod_set_value_cansleep(pcie->pex_prsnt_gpiod, 1);
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gpiod_set_value_cansleep(pcie->pex_prsnt_gpiod, 1);
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}
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}
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enable_irq(pcie->pex_rst_irq);
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return 0;
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return 0;
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}
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}
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static void tegra264_pcie_ep_stop(struct pci_epc *epc)
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static void tegra264_pcie_ep_stop(struct pci_epc *epc)
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{
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{
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struct tegra264_pcie_ep *pcie = epc_get_drvdata(epc);
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struct tegra264_pcie_ep *pcie = epc_get_drvdata(epc);
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disable_irq(pcie->pex_rst_irq);
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if (pcie->pex_prsnt_gpiod) {
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if (pcie->pex_prsnt_gpiod) {
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dev_dbg(pcie->dev, "Asserting PRSNT\n");
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dev_dbg(pcie->dev, "Asserting PRSNT\n");
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@@ -717,6 +720,7 @@ static int tegra264_pcie_ep_probe(struct platform_device *pdev)
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dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret);
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dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret);
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return ret;
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return ret;
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}
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}
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disable_irq(pcie->pex_rst_irq);
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pcie->xal_base = devm_platform_ioremap_resource_byname(pdev, "xal");
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pcie->xal_base = devm_platform_ioremap_resource_byname(pdev, "xal");
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if (IS_ERR(pcie->xal_base)) {
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if (IS_ERR(pcie->xal_base)) {
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@@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only*/
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/* Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved */
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/* SPDX-FileCopyrightText: Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.*/
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#ifndef PCIE_TEGRAT264_EP_H
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#ifndef PCIE_TEGRAT264_EP_H
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#define PCIE_TEGRAT264_EP_H
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#define PCIE_TEGRAT264_EP_H
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@@ -438,6 +438,7 @@ static int tegra264_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
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* - reset GPIO is already de-asserted.
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* - reset GPIO is already de-asserted.
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* - pre-conditions met.
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* - pre-conditions met.
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* - pex-prsnt GPIO is de-asserted if specified in CAL_NET_PIF$CalPcieEp.
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* - pex-prsnt GPIO is de-asserted if specified in CAL_NET_PIF$CalPcieEp.
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* - pex-rst-irq is enabled.
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*/
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*/
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static int tegra264_pcie_ep_start(struct pci_epc *epc);
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static int tegra264_pcie_ep_start(struct pci_epc *epc);
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@@ -468,6 +469,7 @@ static int tegra264_pcie_ep_start(struct pci_epc *epc);
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* - De-initialization: Yes
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* - De-initialization: Yes
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*
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*
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* @outcome
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* @outcome
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* - pex-rst-irq is disabled.
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* - pex-prsnt GPIO is de-asserted if specified in CAL_NET_PIF$CalPcieEp.
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* - pex-prsnt GPIO is de-asserted if specified in CAL_NET_PIF$CalPcieEp.
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* - Tegra264 EP controller is de-initialized, if controller is initialized.
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* - Tegra264 EP controller is de-initialized, if controller is initialized.
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*/
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*/
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