PCI: tegra264: Disable RST# IRQ when EP not ready

Enabled RST# IRQ during EP_START after tegra264_pcie_ep_rst_deassert is
invoked for EP and disable RST# IRQ during EP_STOP after
tegra264_pcie_ep_rst_assert is executed for EP and EP is not available
anymore. This prevents unwanted EP accesses during RP reset sequence
causing PERST# to toggle, while EP is not ready or available.

Bug 5281037

Change-Id: I43e1fd6c6ccfaae64a6bb2375a3685f186766d78
Signed-off-by: Prakhar Srivastava <prasrivastav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3363313
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
This commit is contained in:
Prakhar Srivastava
2025-05-13 12:16:00 +00:00
committed by Jon Hunter
parent 9c6469ff98
commit e6a11f7e4c
2 changed files with 8 additions and 2 deletions

View File

@@ -545,12 +545,15 @@ static int tegra264_pcie_ep_start(struct pci_epc *epc)
gpiod_set_value_cansleep(pcie->pex_prsnt_gpiod, 1); gpiod_set_value_cansleep(pcie->pex_prsnt_gpiod, 1);
} }
enable_irq(pcie->pex_rst_irq);
return 0; return 0;
} }
static void tegra264_pcie_ep_stop(struct pci_epc *epc) static void tegra264_pcie_ep_stop(struct pci_epc *epc)
{ {
struct tegra264_pcie_ep *pcie = epc_get_drvdata(epc); struct tegra264_pcie_ep *pcie = epc_get_drvdata(epc);
disable_irq(pcie->pex_rst_irq);
if (pcie->pex_prsnt_gpiod) { if (pcie->pex_prsnt_gpiod) {
dev_dbg(pcie->dev, "Asserting PRSNT\n"); dev_dbg(pcie->dev, "Asserting PRSNT\n");
@@ -717,6 +720,7 @@ static int tegra264_pcie_ep_probe(struct platform_device *pdev)
dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret); dev_err(dev, "Failed to request IRQ for PERST: %d\n", ret);
return ret; return ret;
} }
disable_irq(pcie->pex_rst_irq);
pcie->xal_base = devm_platform_ioremap_resource_byname(pdev, "xal"); pcie->xal_base = devm_platform_ioremap_resource_byname(pdev, "xal");
if (IS_ERR(pcie->xal_base)) { if (IS_ERR(pcie->xal_base)) {

View File

@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only*/
/* Copyright (c) 2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved */ /* SPDX-FileCopyrightText: Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.*/
#ifndef PCIE_TEGRAT264_EP_H #ifndef PCIE_TEGRAT264_EP_H
#define PCIE_TEGRAT264_EP_H #define PCIE_TEGRAT264_EP_H
@@ -438,6 +438,7 @@ static int tegra264_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
* - reset GPIO is already de-asserted. * - reset GPIO is already de-asserted.
* - pre-conditions met. * - pre-conditions met.
* - pex-prsnt GPIO is de-asserted if specified in CAL_NET_PIF$CalPcieEp. * - pex-prsnt GPIO is de-asserted if specified in CAL_NET_PIF$CalPcieEp.
* - pex-rst-irq is enabled.
*/ */
static int tegra264_pcie_ep_start(struct pci_epc *epc); static int tegra264_pcie_ep_start(struct pci_epc *epc);
@@ -468,6 +469,7 @@ static int tegra264_pcie_ep_start(struct pci_epc *epc);
* - De-initialization: Yes * - De-initialization: Yes
* *
* @outcome * @outcome
* - pex-rst-irq is disabled.
* - pex-prsnt GPIO is de-asserted if specified in CAL_NET_PIF$CalPcieEp. * - pex-prsnt GPIO is de-asserted if specified in CAL_NET_PIF$CalPcieEp.
* - Tegra264 EP controller is de-initialized, if controller is initialized. * - Tegra264 EP controller is de-initialized, if controller is initialized.
*/ */