From e97dbc8de1724be6881d63447a16bfb501ebd215 Mon Sep 17 00:00:00 2001 From: Narayan Reddy Date: Fri, 30 Aug 2019 22:10:57 +0530 Subject: [PATCH] nvethernet: allow PHY read/write if MAC clks enabled Issue: During system suspend, PHY framework is trying to access the PHY registers even though the ethernet interface is not up which inturn causing the bus errors since MAC clocks not enabled. Fix: Add MAC clocks enable check before accessing the PHY registers through MDIO bus. Bug 200548320 Change-Id: Ic85ae82bbc7e7f33203cc94f8407bdfd23f75502 Signed-off-by: Narayan Reddy Reviewed-on: https://git-master.nvidia.com/r/2187285 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../net/ethernet/nvidia/nvethernet/ether_linux.c | 15 +++++++++++++++ .../net/ethernet/nvidia/nvethernet/ether_linux.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c index 04bdb442..1a2ab86b 100644 --- a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c +++ b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.c @@ -49,6 +49,7 @@ static void ether_disable_clks(struct ether_priv_data *pdata) if (!IS_ERR_OR_NULL(pdata->pllrefe_clk)) { clk_disable_unprepare(pdata->pllrefe_clk); } + pdata->clks_enable = false; } /** @@ -107,6 +108,8 @@ static int ether_enable_clks(struct ether_priv_data *pdata) } } + pdata->clks_enable = true; + return 0; err_tx: @@ -2279,6 +2282,12 @@ static int ether_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, struct net_device *ndev = bus->priv; struct ether_priv_data *pdata = netdev_priv(ndev); + if (!pdata->clks_enable) { + dev_err(pdata->dev, + "%s:No clks available, skipping PHY write\n", __func__); + return -ENODEV; + } + return osi_write_phy_reg(pdata->osi_core, (unsigned int)phyaddr, (unsigned int)phyreg, phydata); } @@ -2303,6 +2312,12 @@ static int ether_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) struct net_device *ndev = bus->priv; struct ether_priv_data *pdata = netdev_priv(ndev); + if (!pdata->clks_enable) { + dev_err(pdata->dev, + "%s:No clks available, skipping PHY read\n", __func__); + return -ENODEV; + } + return osi_read_phy_reg(pdata->osi_core, (unsigned int)phyaddr, (unsigned int)phyreg); } diff --git a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h index 9c34e528..0d8cdabb 100644 --- a/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h +++ b/drivers/net/ethernet/nvidia/nvethernet/ether_linux.h @@ -298,6 +298,8 @@ struct ether_priv_data { unsigned int max_platform_mtu; /** Spin lock for PTP registers */ raw_spinlock_t ptp_lock; + /** Clocks enable check */ + bool clks_enable; }; /**