From ea0f4f6a26b93a7dc03f92016408995de63a69d1 Mon Sep 17 00:00:00 2001
From: Brad Griffis <bgriffis@nvidia.com>
Date: Tue, 2 Aug 2022 18:13:38 +0000
Subject: [PATCH] gpu: host1x: ADD SID information for Tegra234 DLA

Add the SMMU SID information for the Tegra234 DLA devices to the
upstream host1x driver to ensure the SMMU is configured correctly.

Bug 3724727

Change-Id: I01edf2bc36f2b8a4b83077fc71f42463f9958a3d
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2754962
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
---
 drivers/gpu/host1x/dev.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index b2e8dc77..8bef2289 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -2,7 +2,7 @@
 /*
  * Tegra host1x driver
  *
- * Copyright (c) 2010-2013, NVIDIA Corporation.
+ * Copyright (c) 2010-2022, NVIDIA Corporation.
  */
 
 #include <linux/clk.h>
@@ -268,6 +268,30 @@ static const struct host1x_sid_entry tegra234_sid_table[] = {
 		.offset = 0x34,
 		.limit = 0x34
 	},
+	{
+		/* NVDLA channel */
+		.base = 0x17e0,
+		.offset = 0x30,
+		.limit = 0x34
+	},
+	{
+		/* NVDLA MMIO */
+		.base = 0x16d8,
+		.offset = 0x0030,
+		.limit = 0x0034
+	},
+	{
+		/* NVDLA1 channel */
+		.base = 0x17e8,
+		.offset = 0x30,
+		.limit = 0x34
+	},
+	{
+		/* NVDLA1 MMIO */
+		.base = 0x16e0,
+		.offset = 0x0030,
+		.limit = 0x0034
+	},
 };
 
 static const struct host1x_info host1x08_info = {