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dtb: disp: Add display node to concord overlay dtb

Browse Source 
This CL creates a dtsi file for display related nodes (dce/display)
It also cretes a dtsi file for dcb display blob.

Bug 3713048

Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com>
Change-Id: I549fd9d78cd4e771d6b8fd893a2d43f2cff83f75
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2795787
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Mahesh Kumar
2022-10-20 21:57:30 +05:30
committed by mobile promotions
parent ddd988fbf6
commit f23cc48733
6 changed files with 770 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

551
arch/arm64/boot/dts/nvidia/tegra234-dcb-p3737-0000-p3701-0000.dtsi Normal file
View File

@@ -0,0 +1,551 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
/ {
fragment-t234-dcb@0 {
target-path = "/";
__overlay__ {
display@13800000 {
nvidia,dcb-image = [
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00 00 03 00 44 0d 00 00 01 0a 08 0f 46 40 00 00
03 00 44 0e 00 00 01 0a 05 0f 46 40 00 00 03 00
44 0f 01 00 01 0a 05 0f 46 40 00 00 03 00 44 10
01 00 01 0a 08 0f 46 40 00 00 03 00 44 7a 14 c0
61 40 01 00 c2 0d 74 05 00 6e 14 c0 61 40 ff ff
bf ff 00 00 00 00 6e e4 c5 61 40 fe ff ff ff 00
00 00 00 71 5b f5 19 71 5b 6f 17 5b 74 17 71 56
00 ff 72 71 6e 0c c1 61 40 fe ff ff ff 00 00 00
00 6e 40 65 61 80 fe ff ff ff 00 00 00 00 71 6e
00 23 61 40 ff ff 80 fc 00 00 23 00 71 6e 00 23
61 40 ff ff 80 fc 00 00 27 00 71 6e 00 23 61 40
ff ff 80 fc 00 00 2b 00 71 6e 00 23 61 40 ff ff
80 fc 00 00 2f 00 71 41 23 10 08 6a 18 cb bd dc
4e 5c 08 00 00 00 00 00 00 ac 18 31 19 c1 00 00
00 00 00 00 00 00 00 00 00 00 06 03 80 01 10 00
60 04 02 03 80 01 10 00 02 04 2e 23 02 01 10 00
02 00 2f 32 03 02 10 00 02 00 fe 40 04 00 00 00
00 00 0f 00 00 00 00 00 00 00 0f 00 00 00 00 00
00 00 0f 00 00 00 00 00 00 00 0f 00 00 00 00 00
00 00 0f 00 00 00 00 00 00 00 0f 00 00 00 00 00
00 00 0f 00 00 00 00 00 00 00 0f 00 00 00 00 00
00 00 0f 00 00 00 00 00 00 00 0f 00 00 00 00 00
00 00 0f 00 00 00 00 00 00 00 41 06 0f 04 02 0f
06 00 00 10 ff 03 00 80 ff 03 00 80 ff 03 00 10
ff 03 00 10 ff 03 00 10 ff 03 00 10 ff 03 00 10
ff 03 00 10 ff 03 00 10 ff 03 00 00 ff 03 00 00
ff 03 00 00 ff 03 00 00 ff 03 00 00 40 05 20 04
01 ff 00 00 00 ff 00 00 00 ff 00 00 00 ff 00 00
00 ff 00 00 00 ff 00 00 00 ff 00 00 00 ff 00 00
00 ff 00 00 00 ff 00 00 00 ff 00 00 00 ff 00 00
00 ff 00 00 00 ff 00 00 00 ff 00 00 00 ff 00 00
00 ff 00 00 00 ff 00 00 00 ff 00 00 00 ff 00 00
00 ff 00 00 00 ff 00 00 00 ff 00 00 00 ff 00 00
00 ff 00 00 00 ff 00 00 00 ff 00 00 00 ff 00 00
00 ff 00 00 00 ff 00 00 00 ff 00 00 00 ff 00 00
00 40 05 10 04 00 46 10 00 00 ff 01 00 00 ff 02
00 00 ff 03 00 00 ff 04 00 00 ff 00 00 00 ff 00
00 00 ff 00 00 00 ff 00 00 00 ff 00 00 00 ff 00
00 00 ff 00 00 00 ff 00 00 00 ff 00 00 00 ff 00
00 00 ff 00 00 00 10 05 40 01 00 00 00 0b 03 00
00 0a 02 00 00 08 02 00 20 04 02 00 80 00 00 00
80 00 00 00 80 00 00 00 80 00 00 00 20 00 00 00
20 00 03 00 00 0c 03 00 00 0a 03 00 80 0b 03 00
80 0b 03 00 80 0b 03 00 80 0b 03 71 71 6e 14 c0
61 40 ff ff 3f fa 00 00 c0 01 74 05 00 6e 14 c0
61 40 f7 ff ff ff 08 00 00 00 6e b8 c1 61 40 ff
ff 3f 81 00 03 00 08 6e 00 23 61 40 ff ff 83 fc
00 00 00 00 71 58 40 c0 61 40 10 00 00 0a 1d 00
00 0a 04 00 00 08 04 00 20 04 04 00 80 00 00 00
80 00 00 00 80 00 00 00 80 00 00 00 20 00 00 00
20 00 1d 00 00 0c 1d 00 00 0a 1d 00 80 0a 1d 00
80 0a 1d 00 80 0a 1d 00 80 0a 1d 71 6e 00 23 61
40 ff ff fc fc 00 00 02 03 71 7a 14 c0 61 40 14
00 c2 0d 74 05 00 6e 14 c0 61 40 ff ff bf ff 00
00 00 00 74 14 00 71 6e 14 c0 61 40 ff ff ff f2
00 00 00 00 74 0a 00 6e 00 23 61 40 ff ff fc ff
00 00 01 00 6e 0c c1 61 60 ff bf ff ff 00 40 00
00 6e 14 c0 61 40 ff ff 7f ff 00 00 00 00 6e 30
c1 61 60 f0 ff ff ff 0f 00 00 00 6e 34 c0 61 40
ff ff ee 7f 00 00 00 80 56 17 ff 6e 0c c1 61 60
fc ff ff ff 01 00 00 00 6e 30 c1 61 60 0f ff ff
ff f0 00 00 00 74 0a 00 6e 30 c1 61 60 0f ff ff
ff 00 00 00 00 6e 10 c1 61 40 e0 e0 e0 e0 00 00
00 00 6e 2c c1 61 40 e0 e0 e0 e0 00 00 00 00 3a
05 15 6e 40 c1 61 60 fd ff ff ff 02 00 00 00 98
0a 01 00 00 01 fe 01 71 98 02 01 00 00 01 d0 00
6e 10 c1 61 40 e0 e0 e0 e0 10 10 10 10 6e 2c c1
61 40 e0 e0 e0 e0 10 10 10 10 71 5f 0c c1 61 60
00 01 40 ff 40 00 00 00 00 40 65 61 80 fe bf 00
bf 3a 00 03 5b 59 1b 72 71 3a 07 01 38 6e 40 c1
61 60 fe ff ff ff 01 00 00 00 72 5b ad 1c 52 e8
df 00 71 71 6e 0c c1 61 60 fe ff 00 ff 00 00 00
00 6e 30 c1 61 40 f0 ff ff ff 00 00 00 00 6e b0
c1 61 40 f0 ff ff ff 00 00 00 00 6e 34 c0 61 40
ff ff ee 7f 00 00 11 80 56 17 ff 6e 14 c0 61 40
ff ff 7f ff 00 00 80 00 6e 00 23 61 40 ff ff fc
ff 00 00 02 00 74 05 00 6e 14 c0 61 40 ff ff ff
f2 00 00 00 0d 74 05 00 6e 14 c0 61 40 ff ff bf
ff 00 00 40 00 74 05 00 6e 14 c0 61 40 f7 ff ff
ff 08 00 00 00 6e 0c c0 61 40 ff f0 f0 f0 00 03
05 05 6e b8 c1 61 40 ff ff ff 81 00 03 00 08 6e
00 23 61 40 ff ff 83 fc 00 00 00 00 6e 40 c1 61
60 fe ff ff ff 00 00 00 00 71 6e 0c c1 61 60 fd
ff ff ff 02 00 00 00 6e 30 c1 61 60 ff ff bf ff
00 00 40 00 71 10 05 40 01 01 00 00 00 00 0a 10
00 00 00 a0 40 00 00 80 40 00 00 80 40 00 00 80
40 00 00 80 40 00 00 80 40 00 00 20 00 00 32 10
80 00 0a 90 80 00 00 80 80 00 00 80 80 00 00 80
80 00 00 80 80 00 00 80 80 00 71 71 6e 40 65 61
80 fe ff ff ff 00 00 00 00 71 71 98 07 01 00 00
01 ef 10 71 98 07 01 00 00 01 ef 00 71 58 40 c0
61 40 10 00 00 00 00 32 10 00 00 00 a0 40 00 00
80 40 00 00 80 40 00 00 80 40 00 00 80 40 00 00
80 40 00 00 20 00 00 32 10 80 00 96 90 80 00 00
80 80 00 00 80 80 00 00 80 80 00 00 80 80 00 00
80 80 00 71 42 15 02 07 13 04 03 0a 04 28 23 28
23 01 04 04 06 45 1c 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 14 00 02 19 0a 03 1e 14 04
2b 28 06 1e 00 03 25 0f 04 2f 21 06 28 00 04 32
14 06 3c 00 06 14 00 02 19 0a 03 1e 14 04 2b 28
06 1e 00 03 25 0f 04 2f 21 06 28 00 04 32 14 06
3c 00 06 14 00 02 19 0a 03 1e 14 04 2b 28 06 1e
00 03 25 0f 04 2f 21 06 28 00 04 32 14 06 3c 00
06 0f 00 02 16 09 03 1d 0e 04 27 12 06 17 00 03
21 09 04 27 0e 06 1f 00 04 27 09 06 27 00 06 a7
1d 00 00 2f 1e 00 00 b7 1e 00 00 3f 1f 00 00 c7
1f 00 00 4f 20 00 00 10 08 00 00 00 10 08 00 1e
00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 14
00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 10
00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 0c
00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 0a
00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 09
00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 08
00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 06
00 00 00 00 01 05 05 00 40 00 00 00 00 00 30 10
08 00 00 00 10 08 00 1e 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 14 00 00 00 00 00 05 05 00
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50 00 00 00 00 00 00 0c 00 00 00 00 03 00 01 00
50 00 00 00 00 00 00 0a 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 09 00 00 00 00 03 00 01 00
40 00 00 00 00 00 00 08 00 00 00 00 03 00 01 00
40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 10 08 00 00 00 10 08 00 1e
00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 14
00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0c
00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0a
00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 09
00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 08
00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 06
00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
08 00 00 00 10 08 00 1e 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 14 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 10 00 00 00 00 03 00 01 00
50 00 00 00 00 00 00 0c 00 00 00 00 03 00 01 00
50 00 00 00 00 00 00 0a 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 09 00 00 00 00 03 00 01 00
40 00 00 00 00 00 00 08 00 00 00 00 03 00 01 00
40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 10 08 00 00 00 10 08 00 1e
00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 14
00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0c
00 00 00 00 03 00 01 00 50 00 00 00 00 00 00 0a
00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 09
00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 08
00 00 00 00 03 00 01 00 40 00 00 00 00 00 00 06
00 00 00 00 00 05 05 00 00 00 00 00 00 00 00 10
08 00 00 00 10 08 00 1e 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 14 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 10 00 00 00 00 03 00 01 00
50 00 00 00 00 00 00 0c 00 00 00 00 03 00 01 00
50 00 00 00 00 00 00 0a 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 09 00 00 00 00 03 00 01 00
40 00 00 00 00 00 00 08 00 00 00 00 03 00 01 00
40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 ];
};
};
};
};

3
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000-overlay.dts
View File

@@ -10,6 +10,8 @@
#include "tegra234-p3701-0000-overlay.dtsi" #include "tegra234-p3701-0000-overlay.dtsi"
#include "tegra234-audio-dai-links-overlay.dtsi" #include "tegra234-audio-dai-links-overlay.dtsi"
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ { / {
fragment-t234-p3737-p3701@0 { fragment-t234-p3737-p3701@0 {
target-path = "/bpmp/i2c"; target-path = "/bpmp/i2c";
@@ -59,6 +61,7 @@
fragment-t234-p3737-p3701@5 { fragment-t234-p3737-p3701@5 {
target-path = "/bus@0/i2c@31b0000"; target-path = "/bus@0/i2c@31b0000";
__overlay__ { __overlay__ {
nvidia,hw-instance-id = <0x5>;
status = "okay"; status = "okay";
}; };
}; };

190
arch/arm64/boot/dts/nvidia/tegra234-soc-display-overlay.dtsi Normal file
View File

@@ -0,0 +1,190 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include <dt-bindings/memory/tegra234-smmu-streamid.h>
#include <dt-bindings/soc/tegra234-powergate.h>
#include <dt-bindings/clock/tegra234-clock-oot.h>
#include <dt-bindings/reset/tegra234-reset-oot.h>
#include <dt-bindings/memory/tegra234-mc-oot.h>
/ {
fragment-t234-display@0 {
target-path = "/";
__overlay__ {
dce@d800000 {
compatible = "nvidia,tegra234-dce";
reg = <0x0 0x0d800000 0x0 0x00800000>;
interrupts =
<0 376 0x4>,
<0 377 0x4>;
interrupt-names = "wdt-remote",
"dce-sm0";
iommus = <&smmu_niso0 TEGRA234_SID_DCE>;
status = "okay";
};
display@13800000 {
compatible = "nvidia,tegra234-display";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
nvidia,num-dpaux-instance = <1>;
reg-names = "nvdisplay", "dpaux0", "hdacodec", "mipical";
reg = <0x0 0x13800000 0x0 0xEFFFF /* nvdisplay */
0x0 0x155C0000 0x0 0xFFFF /* dpaux0 */
0x0 0x0242c000 0x0 0x1000 /* hdacodec */
0x0 0x03990000 0x0 0x10000>; /* mipical */
interrupt-names = "nvdisplay", "dpaux0", "hdacodec";
interrupts = <0 416 4
0 419 4
0 61 4>;
nvidia,bpmp = <&bpmp>;
clocks = <&bpmp TEGRA234_CLK_HUB>,
<&bpmp TEGRA234_CLK_DISP>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P1>,
<&bpmp TEGRA234_CLK_DPAUX>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_DSIPLL_VCO>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTPN>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_VCO>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTB>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV10>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV25>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV27PN>,
<&bpmp TEGRA234_CLK_SPPLL1_VCO>,
<&bpmp TEGRA234_CLK_SPPLL1_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL1_DIV27PN>,
<&bpmp TEGRA234_CLK_VPLL0_REF>,
<&bpmp TEGRA234_CLK_VPLL0>,
<&bpmp TEGRA234_CLK_VPLL1>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0_REF>,
<&bpmp TEGRA234_CLK_RG0>,
<&bpmp TEGRA234_CLK_RG1>,
<&bpmp TEGRA234_CLK_DISPPLL>,
<&bpmp TEGRA234_CLK_DISPHUBPLL>,
<&bpmp TEGRA234_CLK_DSI_LP>,
<&bpmp TEGRA234_CLK_DSI_CORE>,
<&bpmp TEGRA234_CLK_DSI_PIXEL>,
<&bpmp TEGRA234_CLK_PRE_SOR0>,
<&bpmp TEGRA234_CLK_PRE_SOR1>,
<&bpmp TEGRA234_CLK_DP_LINK_REF>,
<&bpmp TEGRA234_CLK_SOR_LINKA_INPUT>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
<&bpmp TEGRA234_CLK_RG0_M>,
<&bpmp TEGRA234_CLK_RG1_M>,
<&bpmp TEGRA234_CLK_SOR0_M>,
<&bpmp TEGRA234_CLK_SOR1_M>,
<&bpmp TEGRA234_CLK_PLLHUB>,
<&bpmp TEGRA234_CLK_SOR0>,
<&bpmp TEGRA234_CLK_SOR1>,
<&bpmp TEGRA234_CLK_SOR_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SF0>,
<&bpmp TEGRA234_CLK_SF0>,
<&bpmp TEGRA234_CLK_SF1>,
<&bpmp TEGRA234_CLK_DSI_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SOR0_REF>,
<&bpmp TEGRA234_CLK_PRE_SOR1_REF>,
<&bpmp TEGRA234_CLK_SOR0_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR1_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR0_REF>,
<&bpmp TEGRA234_CLK_SOR1_REF>,
<&bpmp TEGRA234_CLK_OSC>,
<&bpmp TEGRA234_CLK_DSC>,
<&bpmp TEGRA234_CLK_MAUD>,
<&bpmp TEGRA234_CLK_AZA_2XBIT>,
<&bpmp TEGRA234_CLK_AZA_BIT>,
<&bpmp TEGRA234_CLK_MIPI_CAL>,
<&bpmp TEGRA234_CLK_UART_FST_MIPI_CAL>,
<&bpmp TEGRA234_CLK_SOR0_DIV>;
clock-names = "nvdisplayhub_clk",
"nvdisplay_disp_clk",
"nvdisplay_p0_clk",
"nvdisplay_p1_clk",
"dpaux0_clk",
"fuse_clk",
"dsipll_vco_clk",
"dsipll_clkoutpn_clk",
"dsipll_clkouta_clk",
"sppll0_vco_clk",
"sppll0_clkoutpn_clk",
"sppll0_clkouta_clk",
"sppll0_clkoutb_clk",
"sppll0_div10_clk",
"sppll0_div25_clk",
"sppll0_div27_clk",
"sppll1_vco_clk",
"sppll1_clkoutpn_clk",
"sppll1_div27_clk",
"vpll0_ref_clk",
"vpll0_clk",
"vpll1_clk",
"nvdisplay_p0_ref_clk",
"rg0_clk",
"rg1_clk",
"disppll_clk",
"disphubpll_clk",
"dsi_lp_clk",
"dsi_core_clk",
"dsi_pixel_clk",
"pre_sor0_clk",
"pre_sor1_clk",
"dp_link_ref_clk",
"sor_linka_input_clk",
"sor_linka_afifo_clk",
"sor_linka_afifo_m_clk",
"rg0_m_clk",
"rg1_m_clk",
"sor0_m_clk",
"sor1_m_clk",
"pllhub_clk",
"sor0_clk",
"sor1_clk",
"sor_pad_input_clk",
"pre_sf0_clk",
"sf0_clk",
"sf1_clk",
"dsi_pad_input_clk",
"pre_sor0_ref_clk",
"pre_sor1_ref_clk",
"sor0_ref_pll_clk",
"sor1_ref_pll_clk",
"sor0_ref_clk",
"sor1_ref_clk",
"osc_clk",
"dsc_clk",
"maud_clk",
"aza_2xbit_clk",
"aza_bit_clk",
"mipi_cal_clk",
"uart_fst_mipi_cal_clk",
"sor0_div_clk";
resets = <&bpmp TEGRA234_RESET_NVDISPLAY>,
<&bpmp TEGRA234_RESET_DPAUX>,
<&bpmp TEGRA234_RESET_DSI_CORE>,
<&bpmp TEGRA234_RESET_MIPI_CAL>;
reset-names = "nvdisplay_reset",
"dpaux0_reset",
"dsi_core_reset",
"mipi_cal_reset";
status = "okay";
nvidia,disp-sw-soc-chip-id = <0x2350>;
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR>,
<&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR1>;
interconnect-names = "dma-mem", "read-1";
#endif
iommus = <&smmu_iso TEGRA234_SID_ISO_NVDISPLAY>;
non-coherent;
nvdisplay-niso {
compatible = "nvidia,tegra234-display-niso";
iommus = <&smmu_niso0 TEGRA234_SID_NVDISPLAY>;
dma-coherent;
};
};
};
};
};

20
arch/arm64/boot/dts/nvidia/tegra234-soc-overlay.dtsi
View File

@@ -13,6 +13,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/tegra234-gpio.h> #include <dt-bindings/gpio/tegra234-gpio.h>
#include "tegra234-soc-display-overlay.dtsi"
#define TEGRA234_POWER_DOMAIN_GPU 35U #define TEGRA234_POWER_DOMAIN_GPU 35U
/ { / {
@@ -733,24 +735,6 @@
}; };
}; };
fragment-t234@5 {
target-path = "/";
__overlay__ {
dce@d800000 {
compatible = "nvidia,tegra234-dce";
reg = <0x0 0x0d800000 0x0 0x00800000>;
interrupts =
<0 376 0x4>,
<0 377 0x4>;
interrupt-names = "wdt-remote",
"dce-sm0";
iommus = <&smmu_niso0 TEGRA234_SID_DCE>;
status = "okay";
};
};
};
fragment-t234@6 { fragment-t234@6 {
target-path = "/bus@0/pwm@3280000"; target-path = "/bus@0/pwm@3280000";
__overlay__ { __overlay__ {

2
include/dt-bindings/clock/tegra234-clock-oot.h
View File

@@ -86,6 +86,8 @@
#define TEGRA234_CLK_EXTPERIPH3 38U #define TEGRA234_CLK_EXTPERIPH3 38U
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
#define TEGRA234_CLK_EXTPERIPH4 39U #define TEGRA234_CLK_EXTPERIPH4 39U
/** @brief output of gate CLK_ENB_FUSE */
#define TEGRA234_CLK_FUSE 40U
/** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */ /** @brief output of GPU GPC0 clkGen (in 1x mode same rate as GPC0 MUX2 out) */
#define TEGRA234_CLK_GPC0CLK 41U #define TEGRA234_CLK_GPC0CLK 41U
/** @brief TODO */ /** @brief TODO */

22
include/dt-bindings/soc/tegra234-powergate.h Normal file
View File

@@ -0,0 +1,22 @@
/*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
*
* NVIDIA CORPORATION and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto. Any use, reproduction, disclosure or
* distribution of this software and related documentation without an express
* license agreement from NVIDIA CORPORATION is strictly prohibited.
*/
#ifndef BPMP_ABI_MACH_T234_POWERGATE_T234_H
#define BPMP_ABI_MACH_T234_POWERGATE_T234_H
/**
* @file
* @defgroup bpmp_pdomain_ids Power Domain ID's
* This is a list of power domain IDs provided by the firmware.
* @{
*/
#define TEGRA234_POWER_DOMAIN_DISP 3U
#endif