From f535883c6af462150860490ff751b9f58b239381 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 18 May 2022 13:12:34 +0300 Subject: [PATCH] drm/tegra: Introduce program_iommu_regs helper The VIC and NVDEC drivers contain some duplicated code. Start chipping away at that by introducing a helper for programming the TRANSCFG and STREAMID registers. Bug 3778105 Signed-off-by: Mikko Perttunen Change-Id: I30f9cf3fb8fb89fa5abf5f5e17ba41649a42097e Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2771766 (cherry picked from commit 27872b2f90d66d8706594f5903cff4d2b1e88be4) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2759058 Reviewed-by: Jonathan Hunter GVS: Gerrit_Virtual_Submit Tested-by: Jonathan Hunter --- drivers/gpu/drm/tegra/Makefile | 3 +- drivers/gpu/drm/tegra/nvdec.c | 21 ++------------ drivers/gpu/drm/tegra/util.c | 50 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/util.h | 11 ++++++++ drivers/gpu/drm/tegra/vic.c | 34 ++--------------------- drivers/gpu/drm/tegra/vic.h | 7 ----- 6 files changed, 69 insertions(+), 57 deletions(-) create mode 100644 drivers/gpu/drm/tegra/util.c create mode 100644 drivers/gpu/drm/tegra/util.h diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index 198b1206..05ebf977 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -32,7 +32,8 @@ tegra-drm-next-y := \ vic.o \ nvdec.o \ nvenc.o \ - nvjpg.o + nvjpg.o \ + util.o tegra-drm-next-y += trace.o diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c index c8caf583..3ff40aa0 100644 --- a/drivers/gpu/drm/tegra/nvdec.c +++ b/drivers/gpu/drm/tegra/nvdec.c @@ -20,6 +20,7 @@ #include "drm.h" #include "falcon.h" +#include "util.h" #include "vic.h" #define NVDEC_TFBIF_TRANSCFG 0x2c44 @@ -58,26 +59,10 @@ static inline void nvdec_writel(struct nvdec *nvdec, u32 value, static int nvdec_boot(struct nvdec *nvdec) { -#ifdef CONFIG_IOMMU_API - struct iommu_fwspec *spec = dev_iommu_fwspec_get(nvdec->dev); -#endif int err; -#ifdef CONFIG_IOMMU_API - if (nvdec->config->supports_sid && spec) { - u32 value; - - value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | TRANSCFG_ATT(0, TRANSCFG_SID_HW); - nvdec_writel(nvdec, value, NVDEC_TFBIF_TRANSCFG); - - if (spec->num_ids > 0) { - value = spec->ids[0] & 0xffff; - - nvdec_writel(nvdec, value, VIC_THI_STREAMID0); - nvdec_writel(nvdec, value, VIC_THI_STREAMID1); - } - } -#endif + if (nvdec->config->supports_sid) + tegra_drm_program_iommu_regs(nvdec->dev, nvdec->regs, NVDEC_TFBIF_TRANSCFG); err = falcon_boot(&nvdec->falcon); if (err < 0) diff --git a/drivers/gpu/drm/tegra/util.c b/drivers/gpu/drm/tegra/util.c new file mode 100644 index 00000000..01181c54 --- /dev/null +++ b/drivers/gpu/drm/tegra/util.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, NVIDIA Corporation. + */ + +#include +#include + +#include "util.h" + +#define THI_STREAMID0 0x30 +#define THI_STREAMID1 0x34 + +#define TRANSCFG_ATT(i, v) (((v) & 0x3) << (i * 4)) +#define TRANSCFG_SID_HW 0 +#define TRANSCFG_SID_PHY 1 +#define TRANSCFG_SID_FALCON 2 + +void tegra_drm_program_iommu_regs(struct device *dev, void __iomem *regs, u32 transcfg_offset) +{ +#ifdef CONFIG_IOMMU_API + struct iommu_fwspec *spec = dev_iommu_fwspec_get(dev); + + if (spec) { + u32 value; + + value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | + TRANSCFG_ATT(0, TRANSCFG_SID_HW); + writel(value, regs + transcfg_offset); + + if (spec->num_ids > 0) { + value = spec->ids[0] & 0xffff; + + /* + * STREAMID0 is used for input/output buffers. + * Initialize it to the firmware stream ID in case context isolation + * is not enabled, and the firmware stream ID is used for both firmware + * and data buffers. + * + * If context isolation is enabled, it will be + * overridden by the SETSTREAMID opcode as part of each job. + */ + writel(value, regs + THI_STREAMID0); + + /* STREAMID1 is used usually for firmware loading. */ + writel(value, regs + THI_STREAMID1); + } + } +#endif +} diff --git a/drivers/gpu/drm/tegra/util.h b/drivers/gpu/drm/tegra/util.h new file mode 100644 index 00000000..d60912ef --- /dev/null +++ b/drivers/gpu/drm/tegra/util.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022, NVIDIA Corporation. + */ + +#ifndef DRM_TEGRA_UTIL_H +#define DRM_TEGRA_UTIL_H + +void tegra_drm_program_iommu_regs(struct device *dev, void __iomem *regs, u32 transcfg_offset); + +#endif diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c index 5296a526..15941fde 100644 --- a/drivers/gpu/drm/tegra/vic.c +++ b/drivers/gpu/drm/tegra/vic.c @@ -21,6 +21,7 @@ #include "drm.h" #include "falcon.h" +#include "util.h" #include "vic.h" struct vic_config { @@ -57,41 +58,12 @@ static void vic_writel(struct vic *vic, u32 value, unsigned int offset) static int vic_boot(struct vic *vic) { -#ifdef CONFIG_IOMMU_API - struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev); -#endif u32 fce_ucode_size, fce_bin_data_offset; void *hdr; int err = 0; -#ifdef CONFIG_IOMMU_API - if (vic->config->supports_sid && spec) { - u32 value; - - value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | - TRANSCFG_ATT(0, TRANSCFG_SID_HW); - vic_writel(vic, value, VIC_TFBIF_TRANSCFG); - - if (spec->num_ids > 0) { - value = spec->ids[0] & 0xffff; - - /* - * STREAMID0 is used for input/output buffers. - * Initialize it to SID_VIC in case context isolation - * is not enabled, and SID_VIC is used for both firmware - * and data buffers. - * - * If context isolation is enabled, it will be - * overridden by the SETSTREAMID opcode as part of - * each job. - */ - vic_writel(vic, value, VIC_THI_STREAMID0); - - /* STREAMID1 is used for firmware loading. */ - vic_writel(vic, value, VIC_THI_STREAMID1); - } - } -#endif + if (vic->config->supports_sid) + tegra_drm_program_iommu_regs(vic->dev, vic->regs, VIC_TFBIF_TRANSCFG); /* setup clockgating registers */ vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) | diff --git a/drivers/gpu/drm/tegra/vic.h b/drivers/gpu/drm/tegra/vic.h index acf35aac..aa6d84e4 100644 --- a/drivers/gpu/drm/tegra/vic.h +++ b/drivers/gpu/drm/tegra/vic.h @@ -13,19 +13,12 @@ /* VIC registers */ -#define VIC_THI_STREAMID0 0x00000030 -#define VIC_THI_STREAMID1 0x00000034 - #define NV_PVIC_MISC_PRI_VIC_CG 0x000016d0 #define CG_IDLE_CG_DLY_CNT(val) ((val & 0x3f) << 0) #define CG_IDLE_CG_EN (1 << 6) #define CG_WAKEUP_DLY_CNT(val) ((val & 0xf) << 16) #define VIC_TFBIF_TRANSCFG 0x00002044 -#define TRANSCFG_ATT(i, v) (((v) & 0x3) << (i * 4)) -#define TRANSCFG_SID_HW 0 -#define TRANSCFG_SID_PHY 1 -#define TRANSCFG_SID_FALCON 2 /* Firmware offsets */