From f66b44645e4a5344f3986f4cb018548da90ddd33 Mon Sep 17 00:00:00 2001 From: Mallikarjun Kasoju Date: Tue, 8 Oct 2024 12:52:21 +0000 Subject: [PATCH] scsi: ufs: Set pll3 rate_b Set PLL3 RATEB rate as 582400000. Bug 4757621 Signed-off-by: Mallikarjun Kasoju Change-Id: I18652261b7224d162a502de3d30e5eb354fd6675 --- drivers/scsi/ufs/ufs-tegra-common.c | 11 +++++++++-- drivers/scsi/ufs/ufs-tegra.h | 1 + 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/ufs/ufs-tegra-common.c b/drivers/scsi/ufs/ufs-tegra-common.c index c0c5750b..3f608095 100644 --- a/drivers/scsi/ufs/ufs-tegra-common.c +++ b/drivers/scsi/ufs/ufs-tegra-common.c @@ -755,6 +755,7 @@ static int ufs_tegra_enable_ufs_uphy_pll3(struct ufs_tegra_host *ufs_tegra, { int err = 0; struct device *dev = ufs_tegra->hba->dev; + unsigned long rate_b_freq; if (!ufs_tegra->configure_uphy_pll3) return 0; @@ -765,9 +766,15 @@ static int ufs_tegra_enable_ufs_uphy_pll3(struct ufs_tegra_host *ufs_tegra, return err; if (is_rate_b) { - if (ufs_tegra->ufs_uphy_pll3) + if (ufs_tegra->ufs_uphy_pll3) { + if (ufs_tegra->soc->chip_id == TEGRA264) + rate_b_freq = UFS_CLK_UPHY_PLL3_RATEB_T264; + else + rate_b_freq = UFS_CLK_UPHY_PLL3_RATEB; + err = clk_set_rate(ufs_tegra->ufs_uphy_pll3, - UFS_CLK_UPHY_PLL3_RATEB); + rate_b_freq); + } } else { if (ufs_tegra->ufs_uphy_pll3) err = clk_set_rate(ufs_tegra->ufs_uphy_pll3, diff --git a/drivers/scsi/ufs/ufs-tegra.h b/drivers/scsi/ufs/ufs-tegra.h index 02d34c9c..3b819248 100644 --- a/drivers/scsi/ufs/ufs-tegra.h +++ b/drivers/scsi/ufs/ufs-tegra.h @@ -163,6 +163,7 @@ /*Uphy pll clock defines*/ #define UFS_CLK_UPHY_PLL3_RATEA 4992000000 #define UFS_CLK_UPHY_PLL3_RATEB 5840000000 +#define UFS_CLK_UPHY_PLL3_RATEB_T264 582400000 /* HS clock frequencies */ #define MPHY_TX_HS_BIT_DIV_CLK 600000000