From f6865a3c2d18f3212b0e67cce7226bc7edebbc9f Mon Sep 17 00:00:00 2001
From: Nikesh Oswal <noswal@nvidia.com>
Date: Wed, 2 Nov 2022 12:37:22 +0000
Subject: [PATCH] gpu: host1x: allow tsec streamid reg access via MMIO

Set Host1X registers to allow both the TSEC StreamID
registers to be programmed via MMIO from the TSEC driver

Bug 3817626

Change-Id: Ic344ecbca557d4c058accc8db1a9f874945e8280
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2801852
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
---
 drivers/gpu/host1x/dev.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 46f143bc..9b375fff 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -388,6 +388,12 @@ static const struct host1x_sid_entry tegra234_sid_table[] = {
 		.offset = 0x34,
 		.limit = 0x34,
 	},
+	{
+		/* TSEC MMIO */
+		.base = 0x16a8,
+		.offset = 0x30,
+		.limit = 0x34,
+	},
 };
 
 static const struct host1x_info host1x08_info = {