nvadsp: Remove ABRIDGE and UNIT_FPGA_RST from DT

Remove redundant DT 'reg' entries ABRIDGE and UNIT_FPGA_RST
and associated code. 0x0 in the reg entry will not be possible
when 'ranges' property explicitly defines the address ranges.

Bug 4164138
Bug 3682950

Change-Id: I4cb11f8d143b1958c586471674e87d1ab243564f
Signed-off-by: Viswanath L <viswanathl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2983548
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Viswanath L
2023-09-21 13:48:57 +00:00
committed by mobile promotions
parent ffdc1ff5c6
commit fa4a7643c5
3 changed files with 0 additions and 35 deletions

View File

@@ -238,11 +238,9 @@ static int __init nvadsp_parse_dt(struct platform_device *pdev)
struct nvadsp_drv_data *drv_data = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
const char *adsp_elf;
u32 *adsp_reset;
u32 *adsp_mem;
int iter;
adsp_reset = drv_data->unit_fpga_reset;
adsp_mem = drv_data->adsp_mem;
for (iter = 0; iter < ADSP_MEM_END; iter++) {
@@ -315,17 +313,6 @@ static int __init nvadsp_parse_dt(struct platform_device *pdev)
&drv_data->adsp_load_timeout))
dev_dbg(dev, "adsp_load_timeout dt not found\n");
if (drv_data->adsp_unit_fpga) {
for (iter = 0; iter < ADSP_UNIT_FPGA_RESET_END; iter++) {
if (of_property_read_u32_index(dev->of_node,
"nvidia,adsp_unit_fpga_reset", iter,
&adsp_reset[iter])) {
dev_err(dev, "adsp reset dt %d not found\n",
iter);
return -EINVAL;
}
}
}
nvadsp_parse_clk_entries(pdev);
if (nvadsp_parse_co_mem(pdev))
@@ -402,17 +389,6 @@ static int __init nvadsp_probe(struct platform_device *pdev)
goto out;
}
if (!drv_data->adsp_unit_fpga && iter == UNIT_FPGA_RST)
continue;
/*
* skip if the particular module is not present in a
* generation, for which the register start address
* is made 0 from dt.
*/
if (res->start == 0)
continue;
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base)) {
dev_err(dev, "Failed to iomap resource reg[%d]\n",

View File

@@ -28,8 +28,6 @@
enum {
AMC,
AMISC,
ABRIDGE,
UNIT_FPGA_RST,
AHSP,
APE_MAX_REG
};
@@ -62,12 +60,6 @@ enum adsp_evp_dt {
ADSP_EVP_END,
};
enum adsp_unit_fpga_reset {
ADSP_ASSERT,
ADSP_DEASSERT,
ADSP_UNIT_FPGA_RESET_END,
};
#define AMISC_REGS 0x2000
#define AMISC_ADSP_L2_REGFILEBASE 0x10
@@ -231,7 +223,6 @@ struct nvadsp_drv_data {
u32 adsp_mem[ADSP_MEM_END];
bool adsp_unit_fpga;
u32 unit_fpga_reset[ADSP_UNIT_FPGA_RESET_END];
u32 agic_irqs[NVADSP_VIRQ_MAX];
struct tegra_bwmgr_client *bwmgr;

View File

@@ -89,7 +89,6 @@ struct nvadsp_debug_log {
};
struct nvadsp_os_data {
void __iomem *unit_fpga_reset_reg;
const struct firmware *os_firmware;
struct platform_device *pdev;
struct global_sym_info *adsp_glo_sym_tbl;
@@ -2596,7 +2595,6 @@ int __init nvadsp_os_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
int ret = 0;
priv.unit_fpga_reset_reg = drv_data->base_regs[UNIT_FPGA_RST];
priv.hwmailbox_base = drv_data->base_regs[hwmb_reg_idx()];
priv.dram_region = drv_data->dram_region;