Summary: Previously mods stored handles for both
clocks and resets in the same list. This meant
reset signals that didn't have a corresponding
clock signal could not be toggled. This change
adds a separate list of structures to handle
resets and decouple it from the clock handling.
Change-Id: I2a83dd5cb7b7fe412acf7ae1815b18b747ad2cac
Signed-off-by: Ellis Roberts <ellisr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2225415
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In git, we have moved this header to uapi directory, so that it can be
installed with the headers_install target. It now has to follow
guidelines of well-formed headers usable in userspace programs.
* Update SPDX license header.
* Don't use kernel CONFIG options.
Bug 2657961
Change-Id: Iee2bbfc6c931b5e8c5ee71cef9dfdfbb7f50d114
Signed-off-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2310801
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Bug 200582229
This change will add smmu mapping/unmapping support for MODS
allocated memory buffer by using kernel smmu api dma_map_sg_attrs()
and dma_unmap_sg_attrs()
1. new IOCTL MODS_ESC_IOMMU_DMA_MAP_MEMORY and
MODS_ESC_IOMMU_DMA_UNMAP_MEMORY is added to do smmu mapping/unmapping
and get smmu mapped address for MODS allocated buffers;
2. a platform device and driver is added to match mods smmu sid in dtb,
the device is used to do smmu mapping/unampping; and mods smmu devices
are added in dtb to match with the driver with smmu config
Signed-off-by: Dong Qiang <carld@nvidia.com>
Change-Id: I47d4d1c43f14fc6b51f0c00cee127e1d51377f64
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2180897
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Updating Kernel 5.15 with recent linux driver changes.
Jira ESSS-504
bug 3979224
Mentioned below are the details of merging changes -
NVVSE: Added support for TSEC algorithm.
- Add support for TSEC CMAC Sign/Verify commands
- Add support for command to check TSEC Keyload status
- Don't use skip_key parameter as keyslot id is always needed by VSE driver
Jira ESSS-267
nvvse: cryptodev: Add support for user nonce
Changes:
- Add support for userNonce and zero copy flag for
TLS and zero copy features
- Updaeted encrypt/decrypt function call to use
user nonce.
Jira ESSS-415
nvvse: Updated IVCCFG offset, IVC DB parameters
- Reading max buffer size and gcm dec buffer size from DT
- Update elements of IVC DB.
Jira ESSS-417
Jira ESSS-484
Jira ESSS-468
bug 3974121
Signed-off-by: Advaya Andhare <aandhare@nvidia.com>
Change-Id: Ic7c4580dc4f443db9f7e4fabfb7ec49de2973ed3
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2862329
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-by: Manish Bhardwaj <mbhardwaj@nvidia.com>
Reviewed-by: Nagaraj P N <nagarajp@nvidia.com>
Reviewed-by: Leo Chiu <lchiu@nvidia.com>
Reviewed-by: Vipin Kumar <vipink@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
nvscic2c enables xfer between two SoC connected over PCIe.
nvscic2c already available with K5.10
Major changes in nvscic2c-pcie for K5.15:
Integrate with upstream PCIe endpoint function changes.
Allocate new IOVA domain to be used for
empty IOVA allocation.
This IOVA range would be used in iommu_map() to map
physical backing with IOMMU domain attached in PCIe device.
Migrate from nvhost to host1x and tegra-drm interfaces.
Bug 3739487
Jira C2C-826
Jira C2C-830
Change-Id: Ic4d8ac680921807fb17247855ca7037623681cb7
Signed-off-by: dbadgaiyan <dbadgaiyan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2810806
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Arihant Jejani <ajejani@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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