1. Add Flag which decides stats work queue is enabled(1) or
disabled(0)
2. If virtualization is enabled then allow function driver instance
to specify non zero DMA channel and to read stats flag from DT.
Bug 2694285
Change-Id: Ic97c079e66c117ed78f1b473ffda33173bd3f23c
Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Change-Id: Ic97c079e66c117ed78f1b473ffda33173bd3f23c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2327179
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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Issue: Deadlock observed because ptp_lock shared
between process context and Interrupt context.
Below is the scenario where deadlock observed -
1) ether_adjust_freq acquired the lock
2) At the same ether_get_ptptime() called from IRQ context
3) ether_adjust_freq() got preempted and ether_get_ptptime()
trying to aquire the lock again which leads to dead lock.
Fix: Disable the interrupts before aquiring the lock
by using IRQ-safe variant of raw spinlock.
Bug 200591192
Bug 200535378
Change-Id: I6f884883bf9cf93877ddb5d0fb7b2927573a1858
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2323211
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Issue: During SOC suspend, the MAC is placed in reset.
This causes all dynamic configurations done by
SW on the MAC core registers is lost. When SOC
resumes, MAC is initialized to power-on-default
configuration, while other SW components still
have previously set configuration. This results
in mismatch between HW/SW configuration.
Fix: Invoke APIs osi_save_registers(), osi_restore_registers()
to backup and restore the MAC core configuration
registers before suspend and after resume respectively.
Bug 200561046
Change-Id: I22183ba86fe9e7a7d8f9efb6a90c265182c5c68a
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2267402
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Issue: osi_process_tx_completions is run in the BH for
processing Tx done irq. This function always loops
till the Tx status for all packets that are Tx'd so
far is processed.
1) The NAPI budget for this Tx completions handler is
not honored.
2) The condition to invoke napi_complete() is incorrect.
Currently, processed count should be 0, which can happen
only if BH is scheduled to run and it finds no packets that
have completed Tx. THis is a wasted schedule for the BH.
3) netdev stats for Tx packets is incremented for every Tx
descriptor instead of packet.
Fix: 1) Add budget parameter to osi_process_tx_completions() API.
2) Change condition to invoke napi_complete() to avoid wasted
scheduling of the napi handler.
3) Increment the netdev stats only when skb is consumed ie.
entire packet is transmitted).
Bug 2756439
Change-Id: I273bdb2667112b8d252b119dee5cc92055cb2913
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2237821
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Issue: When configuring loopback mode, netif_carrier_on/off
APIs are directly used i.e, netif_carrier_on when
loopback mode enabled, netif_carrier_off when
loopback mode is disabled. If anyone enables/disables
loopback mode when link is alreay up, then link is
not restored. Stack is not sending packets due
to netif_carrier_off.
Fix: Check PHY link status before calling netif_carrier_*
APIs. If link is up, then PHY framework would have
already invoked these APIs.
Bug 200512681
Change-Id: I1e07df202a8915737be8992f838aa5bd5534c512
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2267401
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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Issue:
In suspend - PHY placed in reset with phy-reset GPIO.
With this, all register content will be gone.
After resume - PHY placed out of reset but
PHY registers will not be restored. With this change,
we are putting PHY in the proper state after resume.
Fix:
Add PHY config on resume call.
Bug 200545651
Change-Id: I138d951c42be0b00a1e22c2a45f0d58567f22df1
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255706
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Tx frame count and software timer based interrupt coalescing
is enabled. Tx frame count based interrupt coalescing can be
enabled only when tx software timer based interrupt coalescing
is also enabled.
Bug 200529168
Change-Id: I8ac701c86238e8d34d7dbe9924df1162083c023e
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2234610
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Rx frame based coalescing can be enabled only when
Rx timer based coalescing is also enabled. This is to avoid
no rx interrupt issues for applications which send only limited
frames and expects reply.
Bug 200529168
Change-Id: I7b00414bd56935ad8df57c9fa28764feb878213d
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2233503
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Issue:
Data packets sent via EQOS hardware are not
following any packet gaping. The AVB use-cases
have different timing requirements for class A
data packets. For example, the time difference
between two class A data packets are supposed
to be 125 microseconds for audio data
of frequency 48 kHz.
Fix:
Enable slot function support to schedule the data
fetching from the system memory by the DMA.
This feature is useful when the source AV data
needs to be transmitted at specific intervals.
Bug 200545374
Change-Id: I549014998380cd6c0d161c778bccdaa5ed017129
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2223850
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Issue: APIs like osi_clear_tx/rx_intr, osi_update_rx_tailptr
are redundant. The operations that are done in these
functions can be included as part of other existing
OSD-OSI interface API. OSD need not micro-manage the
hardware controller by using such fine grain APIs.
Fix: Remove the redundant APIs and implement their functionality
as part of existing APIs.
Bug 2715391
Change-Id: Ib2feee7b9080d3762ddd33f79f5410ef10a43a07
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2211092
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Issue: Ethtool ops are registered during probe function and can
be invoked by external modules at any time as long as driver
is loaded. Certain ops functions read HW registers from the
MAC controller during function execution. Reading HW stats
is one such ops. However, when interface is down - HW is
placed in reset. Trying to read HW registers results in CBB
errors in this case. Also, the stats maintained in SW structs
are not cleared upon interface down.
Fix: Do not allow reading HW stats when interface is down in the
ethtool ops callback functions. Clear the SW stats structs
when interface is down. There is no need to explicitly
clear the stats in probe as stats memory is already zero
inititalized in probe.
Bug 2732055
Change-Id: I425b473819f170039ff63e6973ff29a0fe4a4e9c
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2221221
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Receive timestamp for a received packet will be in context descriptor
which is immediate of normal descriptor (has valid packet data)
In current case nvethernet driver only unmap normal descriptor buffer
address and provide the buffer to the network stack for data processing.
Context descriptor buffer is not unmapped which leads to running out of
IOVA space for the new buffers.
Context descriptor buffer can be used as is since that is not provided
to the network stack. So this change to skip new buffer allocation and
mapping for the context descriptor which has receive timestamp and use
already allocated buffer.
Bug 2700522
Change-Id: I55ef09286d20262384f792aa8875523ab3d3e9b9
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214732
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Issue: ether_get_ptptime() is registered as a callback
function to read ptp time using tegra_register_hwtime_source.
But it is not unregistered before interface is brought down.
This causes clients to still query for timestamp even though
interface is down and MAC is in reset, resulting in CBB errors.
Fix: Unregister the callback function in ether_close()
Bug 200556936
Change-Id: Idb5b698460f02101c931fd64fbdfc9c06949e05a
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210705
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Issue: In ether_open(), following issues are noted:
1. ether_ptp_init() is called after starting MAC,
which could cause some PTP packets to be missed.
2. napi handlers are not enabled before requesting
irq/starting MAC. This can cause issues if irq is
raised immediately (if irq becomes shared in some
platform) after it is requested.
3. ether_request_irq() is called before DMA resources
are initialized. This will also cause problem if irq
is raised immediately.
Fix: Move and re-order function invocations in ether_open()
so that driver is ready to go (DMA resources allocated,
napi handlers enabled etc.) by the time irq is requested/
MAC is started for Rx/Tx.
Bug 2715330
Change-Id: I491251c8e749ccad2890ad0d113c87aaf3d87b42
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2211091
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
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Issue:
1) Spin locks are used for code path which is already serialized
by network stack
2) On interface down/up, MAC registers are getting reset and
re-initialized but private structure variables are not updated
Fix:
1) Remove spinlocks
2) Re-initialize private structure variables
Bug 200548252
Bug 200547544
Change-Id: Ifb0ce27ba96f8657eebde21e5d02d8b36fb1778b
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189974
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HW MMC registers are 32 bits in size. Some of these will
overrun in few secs if there are live traffic at line rate.
Scheduling work queue to get periodic value from MMC
HW registers and update in 64 bits local variables, will
be solution to this HW limitation.
Bug 200544686
Change-Id: Ifc358f3f6b50839f7d9f48c2f98cb2cdd9ac0821
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2179298
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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