In Orin and previous chipsets, engine timestamp counter
runs 32 times faster than CNTVCT register, so the actual
timestamp is obtained by right shifting with factor of 5.
In Thor onwards, this shift is not required is for VIC engine.
Jira HOSTX-5905
Change-Id: I69980fdfcf50b15db99b1fbad522aecd571a0f17
Signed-off-by: Mainak Sen <msen@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3306825
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Enable CRC generation feature on VIC, OFA, and NVENC where
possible. Whether CRC generation can be enabled depends on
whether the engine's SEC register aperture is writable, based
on platform configuration.
The firewall configuration is for now determined in a hacky
way using ioremap, pending design decisions on how to do it
in a cleaner way.
Bug 4273775
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: Ia7507f4cce2b49703328d5dfdd74aaac8cff8153
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3120662
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
When actmon reports the client usage information, it will call the
get_rate callback provided by the client, and divide the number of
sampled active clock cycles from the actmon counter register with the
current client rate to determine the client usage value.
Bug 4338396
Signed-off-by: Johnny Liu <johnliu@nvidia.com>
Change-Id: I5e3f69b8ed1d90407fe0b8202e7c9cde75a0dd30
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3000330
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Currently, engine drivers only enable runtime PM during the host1x
init callback. This can happen slightly later than the probe, which
can cause the power domain to intermittently not be turned off after
probe.
My hypothesis is that there is a race condition between the post-probe
power domain poweroff that is done from a queued work, and the
pm_runtime_enable call happening in the host1x init callback.
If the pm_runtime_enable call happens first, everything is OK and
the power off work can disable the power domain as PM runtime is
enabled and the device is runtime suspended. If power off work runs
first, PM runtime is still disabled for the device and the domain
must be kept powered.
Resolve the issue by moving the runtime PM enablement to the
probe function.
Bug 3982357
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: I9a10e1dff580affebe05d9cc9ab3e24d1d3ca547
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2859476
Reviewed-by: Santosh BS <santoshb@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Add support for the optical flow accelerator. Implementation is the
same as for other Falcons except that we omit some legacy things
since the engine only exists from T234 onwards, and the addition
of having to initialize the OFA's safety RAM before boot.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: I9612e82a116cc76be492a0c533afce67c42f6a2c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2784964
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
