On Tegra194 the PEQ gain and shift settings are not maintained across
AUD powergate transitions. Simply by reading the gain/shift settings
from userspace via amixer/tinymix continuously causing the AUD powergate
to power cycle the settings can be seen to continuously change.
Commit bc4166782c07 ("tegra-alt: Enable ahubram prog. in hw_params")
partially fix the problem by re-configuring the gain/shift settings to
their default settings each time the PEQ is in-use, however, even with
this change, if the user changes the settings, they are not preserved.
On Tegra186 the PEQ gain and shift settings are not preserved after
transitioning to low power states such as SC7. There is a difference
between the PMC on Tegra186 and Tegra194, such that Tegra194 no longer
supports SRAM retention for the AUD powergate which explains why the
device behave slightly differently.
To ensure that the PEQ gain and shift settings are preserved for all
devices add save and restore helpers and invoke them from the OPE
runtime-pm handlers.
Bug 2072802
Bug 200375657
Change-Id: Ic867bcfd355a50eba8ba538a9471722b824df3c5
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1679636
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Asha Talambedu <atalambedu@nvidia.com>
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add support for 8 channels in PEQ. Add support to
program gain and shift RAMs with integer coefficients
instead of byte arrays.
Fix OPE enable writes to incorrect regmap
Jira EMA-393
Change-Id: Ib509a9f95f4c152c2210f88975a1f7572d79ba08
Reviewed-on: http://git-master/r/1318570
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Hariharan Sivaraman <hariharans@nvidia.com>
Reviewed-by: Nitin Pai <npai@nvidia.com>
- removed snd_soc_codec_set_cache_io function
- use snd_soc_kcontrol_codec instead of snd_kcontrol_chip
- use codec->component.val_bytes instead of codec->val_bytes
- use devm_ioremap_resource instead of devm_request_and_ioremap
- snd_soc_dapm_mux_update_power prototype is changed
Change-Id: Ieb699a0e8a12b341c6823337ef2deb0d99292240
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Set default register values for AHUB modules in regmap. This will
ensure after runtime suspend/resume AHUB register POR values
does not get reset to 0.
Bug 200039212
Change-Id: I38e4c04721450b7511404c0db2911b314b68a880
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/603339
When using RBTREE cache, there can be allocations the first time
a register is accessed. This can cause an attempt to schedule while
atomic in the case that the regmap is using a spinlock. This can be
resolved by using a flat cache.
Bug 200041820
Change-Id: Id69592cd5fadbb5ad9ccfdbb1f184733a332512c
Signed-off-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Reviewed-on: http://git-master/r/552940
