Rx frame based coalescing can be enabled only when
Rx timer based coalescing is also enabled. This is to avoid
no rx interrupt issues for applications which send only limited
frames and expects reply.
Bug 200529168
Change-Id: I7b00414bd56935ad8df57c9fa28764feb878213d
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2233503
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Issue:
Data packets sent via EQOS hardware are not
following any packet gaping. The AVB use-cases
have different timing requirements for class A
data packets. For example, the time difference
between two class A data packets are supposed
to be 125 microseconds for audio data
of frequency 48 kHz.
Fix:
Enable slot function support to schedule the data
fetching from the system memory by the DMA.
This feature is useful when the source AV data
needs to be transmitted at specific intervals.
Bug 200545374
Change-Id: I549014998380cd6c0d161c778bccdaa5ed017129
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2223850
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Issue: APIs like osi_clear_tx/rx_intr, osi_update_rx_tailptr
are redundant. The operations that are done in these
functions can be included as part of other existing
OSD-OSI interface API. OSD need not micro-manage the
hardware controller by using such fine grain APIs.
Fix: Remove the redundant APIs and implement their functionality
as part of existing APIs.
Bug 2715391
Change-Id: Ib2feee7b9080d3762ddd33f79f5410ef10a43a07
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2211092
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Issue: Ethtool ops are registered during probe function and can
be invoked by external modules at any time as long as driver
is loaded. Certain ops functions read HW registers from the
MAC controller during function execution. Reading HW stats
is one such ops. However, when interface is down - HW is
placed in reset. Trying to read HW registers results in CBB
errors in this case. Also, the stats maintained in SW structs
are not cleared upon interface down.
Fix: Do not allow reading HW stats when interface is down in the
ethtool ops callback functions. Clear the SW stats structs
when interface is down. There is no need to explicitly
clear the stats in probe as stats memory is already zero
inititalized in probe.
Bug 2732055
Change-Id: I425b473819f170039ff63e6973ff29a0fe4a4e9c
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2221221
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Receive timestamp for a received packet will be in context descriptor
which is immediate of normal descriptor (has valid packet data)
In current case nvethernet driver only unmap normal descriptor buffer
address and provide the buffer to the network stack for data processing.
Context descriptor buffer is not unmapped which leads to running out of
IOVA space for the new buffers.
Context descriptor buffer can be used as is since that is not provided
to the network stack. So this change to skip new buffer allocation and
mapping for the context descriptor which has receive timestamp and use
already allocated buffer.
Bug 2700522
Change-Id: I55ef09286d20262384f792aa8875523ab3d3e9b9
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214732
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Issue: ether_get_ptptime() is registered as a callback
function to read ptp time using tegra_register_hwtime_source.
But it is not unregistered before interface is brought down.
This causes clients to still query for timestamp even though
interface is down and MAC is in reset, resulting in CBB errors.
Fix: Unregister the callback function in ether_close()
Bug 200556936
Change-Id: Idb5b698460f02101c931fd64fbdfc9c06949e05a
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210705
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Issue: In ether_open(), following issues are noted:
1. ether_ptp_init() is called after starting MAC,
which could cause some PTP packets to be missed.
2. napi handlers are not enabled before requesting
irq/starting MAC. This can cause issues if irq is
raised immediately (if irq becomes shared in some
platform) after it is requested.
3. ether_request_irq() is called before DMA resources
are initialized. This will also cause problem if irq
is raised immediately.
Fix: Move and re-order function invocations in ether_open()
so that driver is ready to go (DMA resources allocated,
napi handlers enabled etc.) by the time irq is requested/
MAC is started for Rx/Tx.
Bug 2715330
Change-Id: I491251c8e749ccad2890ad0d113c87aaf3d87b42
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2211091
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Issue:
1) Spin locks are used for code path which is already serialized
by network stack
2) On interface down/up, MAC registers are getting reset and
re-initialized but private structure variables are not updated
Fix:
1) Remove spinlocks
2) Re-initialize private structure variables
Bug 200548252
Bug 200547544
Change-Id: Ifb0ce27ba96f8657eebde21e5d02d8b36fb1778b
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2189974
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HW MMC registers are 32 bits in size. Some of these will
overrun in few secs if there are live traffic at line rate.
Scheduling work queue to get periodic value from MMC
HW registers and update in 64 bits local variables, will
be solution to this HW limitation.
Bug 200544686
Change-Id: Ifc358f3f6b50839f7d9f48c2f98cb2cdd9ac0821
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2179298
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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Issue: During system suspend, PHY framework is trying to
access the PHY registers even though the ethernet interface
is not up which inturn causing the bus errors since MAC clocks
not enabled.
Fix: Add MAC clocks enable check before accessing the PHY
registers through MDIO bus.
Bug 200548320
Change-Id: Ic85ae82bbc7e7f33203cc94f8407bdfd23f75502
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2187285
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MODS tests use private IOCTL to configure MAC loopback mode.
Add a priv ioctl handler to support this in nvethernet driver.
nvethernet driver also has a sysfs knob to configure loopback.
Bug 2665785
Change-Id: I7f488fe81a0772a0881dbba48592bbcd11205dbf
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166181
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1) Register broadcasting MAC timestamp to clients so that
client can make use of the ptp callback for getting the
timestamp
2) Add private ioctl to read Timestamp information of
both HW PTP time and kernel time
Bug 200512422
Change-Id: I03509cc02f28571108a1061c739840c86f960af4
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161172
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Issue:
1) OSI interface function return value are not validated
2) MTL Q and DMA channel 1:1 mapping check missing
Fix:
1) check for valid return value for such API before proceed
2) check for 1:1 mapping between MTLQs and DMA channels
Bug 200512422
Change-Id: Ib61e6099d2dcdd64cb40a58718b0552fc08efa8e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161185
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Issue:
1) MTL Queue can be in any order in input to DT. If not
initialized sw can crash.
2) Don't use return value of skb_get_queue_mapping as
channel number.
Fix:
1) As MTL Queue sequence is already read, use it for
initialization and storing corresponding configuration.
2) Derive the channel number based on the q index
provided by skb_get_queue_mapping.
Bug 200512422
Change-Id: I145f67ee07101ae69821b5ae4a770e512252985b
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156243
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Issue:
1) EQOS_UDP_FILTERING_CMD: SW check for VLAN Hash Filter hw feature
along with user input.
2) EQOS_UDP_FILTERING_CMD/EQOS_TCP_FILTERING_CMD: SW don't set IPFE bit
in MAC packet filter register.
Fix:
1) No need to check for VLAN hash filter hw feature as Hash
filtering is not supported in SW.
2) Call osi_config_l3_l4_filter_enable if MAC filter register already
not configured for L3/L4 filtering.
Bug 200512422
Change-Id: I2cba199f57b79b7357663d39c8e2281f4b49bda8
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2148361
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Issue: Interface is not up after boot
Fix: in ether_open(), MAC reset called before phy is
out of reset, adding steps to take care of it.
Also added put clks in case of probe failure and remove.
Bug 200512422
Change-Id: Id9da0cf77356cc03aaa69f2420028764ba462d47
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2142245
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Issue: Configure Max MTU size support for specific platform
Fix:
if "nvidia,max_platform_mtu" present in platform DT and less than
MAX_HW_MTU supported
set platform max value from DT
else
default MTU(1500 bytes) will be used as platform max mtu
Bug 2594873
Change-Id: Id9b912a0c797c8cefb4233209b4d38004bcdf840
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137919
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
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Issue: MAC registers are not getting reset on ether_close(),
which lead to old values in MAC registers at the time of
osi_hw_core_init().
Fix: Assert MAC-RST gpio and disable clocks in ether_close().
Enable clock, reset MAC_RST gpio and poll for swr, which will
reset all MAC registers.
Note: To read MAC registers, you must have clocks enable and MAC
out of reset
Bug 200512422
Change-Id: If253eff0ae456702d3cdcbe1f177dd91a5aae20d
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2138031
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Issue: Tegra-eqos thermal cooling device is registered
during driver probe(). Once this registration is done,
callbacks via cooling_device_ops can be invoked at any time.
This implies even if driver is just probed, callbacks can try
to trigger a pad calibration due to temperature change and
result in failure trying to access MAC registers when the
MAC netdev interface is not up.
Fix: Move cooling device register/unregister to ether_open/
ether_close() routines respectively, so that callbacks can
be invoked only when interface is actually up.
Bug 1679250
Change-Id: Iaf181ceb3af4b9def188171606d9a9c141d06ccc
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2138382
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Updated IOCTL path to not get impacted with new API
change. OSI call should be done with correct parameters
1) dma_routing_enable
2) dma_chan and
3) addr_mask (for L2 filtering) to support new IOCTL
4) src_dest (for L2 filtering) to support new IOCTL
Included logic for User priority based RxQ selection. We can have DT
entry "nvidia,rx_queue_prio" to configure this setting
i.e. for valid following Queue mapping
Priorities 6,3 to Queue 3
Priorities 4,5 to Queue 2
Priority 0 to Queue 1 and
Priority 1 to Queue 0.
setting will be nvidia,rx-queue-prio = <0x2 0x1 0x30 0x48>;
If static channel selection, i.e. RXQtoDMA set with value 0x03020100,
Priorities 6,3 to Queue 3 to chan 3
Priorities 4,5 to Queue 2 to chan 2
Priority 0 to Queue 1 to chan 1 and
Priority 1 to Queue 0 to chan 0
else if DCS(dma channel selection) enabled
channel will be selected based on filter rules.
Included logic to take input from User On DCS enable or disable. User can
update dt entry "nvidia,dcs-enable", for dcs enable disable for all queue.
i.e nvidia,dcs-enable = <0x1> will enable DCS for all queue.
Bug 200525721
Change-Id: I4ba820f178b03424d01bb4ddd1f1d6eadde572f7
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133196
GVS: Gerrit_Virtual_Submit
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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These stats are read from MAC HW RMON counters as well as SW controlled
control from Core and DMA path.
ethtool -S <interface> is used to get statistics.
There are 3 stats
1) ether_mmc_counters: EQOS HW counters
2) ether_xtra_stat_counters: SW counters from osi/core
3) ether_xtra_dma_stat_counters: SW counters from osi/dma
Bug 200519211
Change-Id: I5b1b6592541c650f01e845667eca2f5c59bcfd08
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113962
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Ethernet pad calibration needs to be triggered for temperature
changes in steps of 35C from -40C to 110C. In order to get
indication of current operating temperature, register a ethernet
cooling device with thermal zones defined as per above requirement.
When the temperature trips these zones, callback function is invoked
from kernel thermal framework, and ethernet driver can trigger pad
calibration.
Bug 1679250
Change-Id: Iaeccca650e371843fa571f7b368bb5464e106314
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120431
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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1. ARP offload can be configured via private ioctl.
Application requesting the arp offload configuration
should provide the IP address to be configured for
ARP offload via ioctl data struct. Refer to
struct ether_ifr_data and
struct arp_offload_param for details.
2. Tx/Rx Checksum offload can be configured via ethtool
3. TCP Segmentation offload can be configured via ethtool
Bug 2571001
Change-Id: If639ab9049db97f200911af456ddb8cb8433fa12
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109676
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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