- Add debugfs to read the traces
- Add support for trace buffer reading
- Add DLA_REGION_TRACE region
- Use Trace Buffer of size 1MB
- Pass wait param to nvdla_send_cmd() for printf cmd
and correct buffer freeing logic for it.
JIRA DLA-94
Change-Id: I42c0b1cb5b3cb1d4866deb80b7636964795d6de5
Signed-off-by: Amit Sharma (SW-Tegra) <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/1229942
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Increase command timeout as in some cases command
execution may take more time, for example when we
have added debug prints in command execution path.
Change-Id: I5222f58d5cdbc79447679219970a3630e35b2a80
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/1249546
- while submitting a task get a reference for queue and release
reference on task completion.
- this is necessary to avoid freeing of queue on user instance close and
also to avoid reuse of it for by next user
Jira DLA-207
Bug 200246031
Change-Id: If441ad4171acee3550fdbebc887043a971985c88
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1244425
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
- task descriptor has two fields next and sequence which helps engine
scheduler for tracking list of tasks from a given queue.
- 'next' pointer gives next task in queue
- 'sequence' number gives task number
Jira DLA-207
Change-Id: If80d38b01d0b10cea791767ec8d0a3a1787cf645
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1244424
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
GVS: Gerrit_Virtual_Submit
- adds syncpoint<->MSS support for DLA
- register dla enginges with MSS interface during init
- while task submission fetches dma address from interface for a given
syncpoint
- removes temp hack added to use dma address
- remove temp slice syncpoint support added for verification without MSS
support
Jira DLA-100
Change-Id: Iff5665f1aa2fce6f3bfa594e9909ebfc96a916bf
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1242663
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add below information to task descriptor
- Address list
- LUT data
- Dynamic ROI
Jira DLA-176
Change-Id: I067025da34a68a2d81c5e3829ac76c516ed8754b
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/1221382
Use offset and memory handle to calculate IOVA address
for descriptors. It allows using single buffer in user
space for all descriptors.
Jira DLA-176
Change-Id: I141efa7fc8662be8aa4b5c3bd2ea7a369a90769a
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/1220956
Some commands need completion or error notification
from firmware to proceed ahead such as clearing some
resources or reading response from firmware.
Add mechanism to wait for command complete or error
notification from firmware. This add limitation of
handling only one command at a time as there is single
set of registers for command send and response.
Add locking for command send so that only one command
is processed at one time.
Remove wait for idle from ping command and instead
use waiting mechanism.
Clean up task resources if task submit command fails.
Jira DLA-127
Jira DLA-176
Change-Id: I92246c080c730dcae514bcea93b78372799bda4a
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/1219539
- pin mapped operation descriptor buffers during task submission
- get operation descriptors handle from user and pass its IOVA to engine
- pin API returns IOVA for given mem handle
- unpin operation descriptors buffers in task cleanup
Jira DLA-93
Change-Id: I78fb22301ab472685c3bae7c424d75140b814887
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1213761
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
GVS: Gerrit_Virtual_Submit
- add debug macro functions for different debug levels like,
info, function, register access etc.
- add option to print to either on console or trace
- add debugfs to set different debug levels and flag to choose
trace
Jira DLA-134
Jira DLA-135
Jira DLA-136
Change-Id: I4cfbb463a2cf1a47d40dce911c86abb4542f957a
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1203575
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
- fix include files path in makefile
- fix ioctl include header file path
- update comments in doxygen format
add support to submit task to engine as per tasklist
management protocol
- maintain list of tasks under assigned queue with ref counts
- allocates task to maintain list of fences and update them
- dma alloc task descriptor and action list and update them
- submit tasks one by one and send received fence back
to application
- register for syncpoint notifier with nvhost for completion
of fence
- on fence completion interrupt handler, cleanup task
Jira DLA-52
Change-Id: Ibe385f47dc9f17dda79cca3daf29b89218dc7289
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1191495
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
- as falcon may not be in a state to process any more request in poweroff
path, do not send set region command
Jira DLA-19
Change-Id: I7ac858554f769b659d2738f7c8ed48b53cc8ec15
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1197453
- move queue related DLA API's to new file to include task API's
along with
Jira DLA-19
Change-Id: I312e021314a3fb7d03dd31a557fb7cf6d6fc86ca
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1191494
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
- as core driver code is growing, split IOCTL related API's
to new source file.
Jira DLA-19
Change-Id: I42ce24300671392e6ac99fcdae12e2525f74e57e
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1191491
Update set region command as per new interface
Jira DLA-19
Change-Id: Ia171fb89b890f79b8df27785079a00cef7351003
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/1180574
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Fix below warning from sparse checks:
- nvdla/nvdla.c warning: symbol 'nvdla_queue_abort' was not
declared. Should it be static?
- pva/pva.c warning: symbol 'pva_queue_abort' was not declared.
Should it be static?
Bug 200088648
Change-Id: I084156f1b0605008fe9b1dbe534211a682257e2e
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1176532
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
- this adds first IOCTL for NvDLA for ping cmd
- this ping cmd added to make sure that, falcon and memory
read/write are working.
- Through IOCTL, pass ping number to falcon via KMD
- From falcon, for CRC check update mailbox and writeback with
multiplier.
Jira DLA-20
Change-Id: I9cd1bb57d42d00b03907d7cb45750dcec0b2df7b
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1170198
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Fix sparse warning:
nvdla.c:40:1: warning: symbol 'attrs' was not declared.
Should it be static?
Bug 200088648
Change-Id: Ic83c46c938fe82d1e8cbdd7c7e2337b39580cc88
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1167423
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
- this adds falcon interrupt support for NvDLA driver.
- Register device for falcon interrupt
- Allocate dump data region and pass dma addr to falcon
after firmware load
- In ISR, read dump data from a allocated dump region and dump
to console
- During engine power off, free dump region
- add dla KMD<->ucode interface header file for cmd communication.
Jira DLA-45
Jira HOSTX-61
Change-Id: I2163c0e50ce8e2231e185d37bcd3ef8e979f7bdf
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1160994
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
GVS: Gerrit_Virtual_Submit
- add support to boot falcon through nvhost_nvdla_finalize_poweron() PM API.
- nvhost_nvdla_finalize_poweron() called by nvhost as restore start
dev ops
- nvhost_flcn_finalize_poweron() is API provided by falcon framework to
request firmware, parse ucode and boot falcon.
- Specify firmware name in NvDLA device data, which is required for
request_firmware
- Fix Kconfig to enable TEGRA_GRHOST_NVDLA by default
Jira DLA-16
Change-Id: I14791fc1f97c283ff9e9b1890183033bfc4087aa
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1147900
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
private data element of platform data is set during falcon init time.
So remove setting it probe time.
Jira DLA-33
Change-Id: I9807d4520757e8e708b674a1b8f4f95aa24ad526
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1156132
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
- NvDLA is a fixed function accelerator engine for deep learning in
Tegra. Engine supports various layers such as convolution, fully-connected,
activation, pooling and normalization.
- This patch adds minimal support stub for engine for device
initialization.
Jira DLA-5
Change-Id: Iecdd3963a77a2f20979ae412ff2f9388c57a26b1
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/1132605
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Remove dummy makefile to prepare the nvdla folder
to do driver integrations from kernel/nvidia to
kernel/nvidia-oot.
Bug 4038415
Change-Id: I45d8fffc504ab9530718c1fa4f3960037e909f25
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
When one process is trying to duplicate RO handle while other process is
trying to free the same RO handle, then race can occur and second
process can decrement the dma-buf's refcount and it may reach to 0. The
first process can then call get_dma_buf on it, leading to NULL pointer
dereference and ultimately to kernel panic. Fix this by taking an extra
dma-buf refcount before duplicating the handle and then decrease it once
duplication is completed.
Bug 3991243
Change-Id: I99901ce19d8a5d23c5192cb10a17efd2ebaf9d3a
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2865519
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
When the carveout size is changed to 2GB, mem->size << PAGE_SHIFT will
overflow the int limit and get wrapped to negative value. Hence
during freeing bitmap, one of the comparison condition is not meeting,
resulting into not freeing bitmap. Ultimately the entire bitmap get
consumed even though it is expected to have empty bits. Fix this by
typecasting the size to u64.
Bug 3962552
Change-Id: Ieaf93a3a91062d3f630921259aa9b3935853e91c
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2861614
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
There is a potential data race for RO dma-buf in the following scenario:
------------------------------------------------------------------
Process 1 | Process 2 | Process 3 |
------------------------------------------------------------------|
AllocAttr handle H1 | | |
MemMap (H1) | | |
AllocAttr(H2) | | |
MemMap(H2) | | |
id1 = GetSciIpcId(H1)| | |
id2 = GetSciIpcId(H2)|H3=HandleFromSciIpcId | |
id3 = GetSciIpcId(H1)| (id1, RO) |H4=HandleFromSciIpcId|
MemUnmap(H2) |QueryHandlePararms(H3)|(id2, RO) |
MemUnmap(H1) |MemMap(H3) |QueryHandleParams(H4)|
HandleFree(H2) |MemUnmap(H3) |MemMap(H4) |
HandleFree(H1) |HandleFree(H3) |H5=HandleFromSciIpcId|
| |(id3, RO) |
| |QueryHandleParams(H5)|
| |MemMap(H5) |
| |MemUnmap(H4) |
| |MemUnmap(H5) |
| |HandleFree(H4) |
| |HandleFree(H5) |
-------------------------------------------------------------------
The race is happening between the HandleFree(H3) in process 2 and
HandleFromSciIpcId(id3, RO) in process 3. Process 2 tries to free the
H3, and function nvmap_free_handle decrements the RO dma-buf's counter,
so that it reaches 0, but nvmap_dmabuf_release is not called immediately
because of which the process 3 get's false value for the following check
if (is_ro && h->dmabuf_ro == NULL)
It results in calling nvmap_duplicate_handle and then meanwhile function
nvmap_dmabuf_release is called and it makes h->dmabuf_ro to NULL. Hence
get_dma_buf fails with null pointer dereference error.
Fix this issue with following approach:
- Before using dmabuf_ro, take the handle->lock, then check if it is not
NULL.
- If not NULL, then call get_file_rcu on the file associated with RO
dma-buf and check return value.
- If return value is false, then dma-buf's ref counter is zero and it is
going away. So wait until dmabuf_ro is set to NULL; and then create a
new dma-buf for RO.
- Otherwise, use the existing RO dma-buf and decrement the refcount
taken with get_file_rcu.
Bug 3741751
Change-Id: I8987efebc476a794b240ca968b7915b4263ba664
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2850394
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
