The following error is observed when PCIE EP is enabled:
drivers/misc/nvscic2c-pcie/stream-extensions.c:766:23: error: implicit
declaration of function ‘platform_get_drvdata’
Include the appropriate file.
Bug 4456727
Bug 4451567
Change-Id: I46aab2fbd01142b9eb3a5a5d665465c115ddeb47
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3128579
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
In new kernel, need to update vm_flags via kernel
provided function. Otherwise below error is met:
./include/linux/mm_types.h:476:20: note: non-static data member
'vm_flags' declared const here
const vm_flags_t vm_flags;
~~~~~~~~~~~~~~~~~^~~~~~~~
1 error generated.
Bug 4196760
Change-Id: I03455af7ce3623d0d8a0f0cd56d569ef3c7af9ea
Signed-off-by: Bruce Xu <brucex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2938942
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- Ordering between message/data and host1x syncpoints is not enforced
strictly.
- Out of the possible WARs, implement dummy PCIe Read between
data/message write and notifications towards peer / remote post-fences.
- WAR: (IPC/messaging mode)For any UMD produced data towards peer,
before notification is triggered, issue a dummy PCIe read via CPU.
- WAR: (streaming mode)DMA flush-ranges(data), wait for DMA interrupt,
when success issue dummy PCIe reads via CPU on remote post-fences
+ issue CPU PCIe writes on each remote post-fence. To achieve this,
CPU map every imported sync object.
NVIPC-974
Change-Id: Id6711d372c0a35e13e399ffbbcd8efcabf147c56
Signed-off-by: Arihant Jejani <ajejani@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2912894
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Janardhan Reddy A <jreddya@nvidia.com>
Reviewed-by: Vipin Kumar <vipink@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
nvscic2c enables xfer between two SoC connected over PCIe.
nvscic2c already available with K5.10
Major changes in nvscic2c-pcie for K5.15:
Integrate with upstream PCIe endpoint function changes.
Allocate new IOVA domain to be used for
empty IOVA allocation.
This IOVA range would be used in iommu_map() to map
physical backing with IOMMU domain attached in PCIe device.
Migrate from nvhost to host1x and tegra-drm interfaces.
Bug 3739487
Jira C2C-826
Jira C2C-830
Change-Id: Ic4d8ac680921807fb17247855ca7037623681cb7
Signed-off-by: dbadgaiyan <dbadgaiyan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2810806
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Arihant Jejani <ajejani@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
