The current code doesn't notify DCE IPC after DCE IPC is in ACK state
Current Flow:
CPU DCE
1: tegra_ivc_init ---------
2: DCE_ADMIN_CMD_IPC_CREATE tegra_ivc_init
3: --------- tegra_ivc_channel_reset
dce:SIVC_STATE_SYNC
cpu:ESTABLISHED
4: tegra_ivc_reset
dce:SIVC_STATE_SYNC ---------
cpu:SYNC
5: Notify() tegra_ivc_channel_notified
dce:SIVC_STATE_ACK
cpu:SYNC
6: tegra_ivc_notified ---------
dce:SIVC_STATE_ACK
cpu:ESTABLISHED
After Step 6 DCE state is in ACK state and CPU state is in ESTABLISHED
state. As there is no further cpu->dce notification in RM_NOTIFY
channel, dce state stays in the "ACK" state and any attempt to send msg
on RM_NOTIFY channel from dce->cpu fails.
This patch notifies dce after step-6, So dce channel is also in the
"ESTABLISHED" state.
If steps 3-6 get executed in CPU before Step 5 in DCE gets a chance
to execute (DCE is slow), the CPU IPC state will change to "established".
Now when step 5 will execute in DCE, it'll see the CPU state as
"established" so, It'll make the DCE state also "established".
That's how it's working today.
Bug 3861985
Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com>
Change-Id: Ieb13f525d3f81b30aaae848d8d5adb1106856b65
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2840065
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
While MST is used, We get two async msgs from DCE and schedule 2 worker
threads, But during processing (dce_client_process_event_ipc) of these
messages, We are processing all the pending messages in one go. So,
while the second worker thread is scheduled, there is no new message
to read.
This Patch fixes the loop to try reading only when there is a new msg to
read. Also convert info print to debug, to avoid print noise.
Bug 3801736
Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com>
Change-Id: Iddf9ea8f0194539baa8c52616e2f836527400176
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2810440
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- when there are multiple async events back to back from DCE with very
short time gap between 2 events(for example, in case of DP MST,
2 heads could be sending flip event notification back to back at
almost same time), there is a possibility of 2nd async event getting
processed very late when shared mailbox register is set to zero as part
of processing 1st async event and before processing of 2nd async event.
- current change fixes it by processing all pending IVC frames for IPC
channel when processing an async event.
- change few error logs to info logs as these are not actually errors.
Bug 3582863
Bug 3429668
Change-Id: I29b1813bed50c4583e37f02bf656802081ccf9d3
Signed-off-by: Santosh Reddy Galma <galmar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2698560
(cherry picked from commit dd1abfa6eaab6e4f599d8c97bdccc7cbb67e1341)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2700438
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
GVS: Gerrit_Virtual_Submit
Re-organize IPC channel reset and mailbox interrupt handling code to
fix race condition where KMD was receiving new msg from DCE while
processing previous msg and clearing mailbox interrupt as part of it.
which was causing wait_for_ipc to get stuck.
JIRA TDS-6381
Change-Id: Ibd6ab1758d9b5b2e3709a03dadbc84f2585653a4
Signed-off-by: Mahesh Kumar <mahkumar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2460641
Reviewed-by: Santosh Galma <galmar@nvidia.com>
Reviewed-by: Arun Swain <arswain@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
For T23x, we have a separate R5 based cluster
named as Display Controller Engine(DCE) to run
our Display RM code. This driver will run on CPU
with the following functionality:
Via debugfs for test and bring-up purposes:
1. Reads the DCE firmware image into DRAM.
2. Sets up DCE AST to cover the DCE firmware image.
3. Sets up R5 reset vector to point to DCE firmware
entry point
4. Brings DCE out of reset
5. Dumps various regsiters for debug
In production env:
1. Manages interrupts to CPU from DCE
2. Uses bootstrap command interface to define Admin
IPC
3. Locks down bootstrap command interface
4. Uses Admin IPC to define message IPC
5. Uses Admin IPC to define message IPC payload area
6. Uses Admin IPC to set IPC channels
6. Uses Admin IPC to define crashdump area
(optional)
7. Provides IPC interfaces for any DCE Client running
on CCPLEX including Display RM.
8. Uses Admin IPC to set logging level (optional)
This patch puts a framework in place with the
following features :
1. Firmware Loading
2. AST Configuration
3. DCE Reset with EVP Programming
4. Logging Infra
5. Debugfs Support
6. Interrupt Handling
7. Mailbox Programming
8. IPC Programming
9. DCE Client Interface
10. Ftrace Support for debug purposes
Change-Id: Idd28cd9254706c7313f531fcadaa7024a5b344e7
Signed-off-by: Arun Swain <arswain@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-t23x/+/2289865
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Mahesh Kumar <mahkumar@nvidia.com>
Reviewed-by: Santosh Galma <galmar@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Mahesh Kumar <mahkumar@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
