/*
 * Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/clock/tegra194-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/tegra194-mc.h>
#include <dt-bindings/power/tegra194-powergate.h>
#include <dt-bindings/reset/tegra194-reset.h>

/ {
	overlay-name = "Tegra194 Jetson Overlay";
	compatible = "nvidia,tegra194";

	fragment@0 {
		target-path = "/bus@0/host1x@13e00000";
		__overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;

			interrupt-parent = <&gic>;

			ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>,
				 <0x0 0x24f00000 0x0 0x24f00000 0x0 0x00100000>;

			nvdla0@15880000 {
				compatible = "nvidia,tegra194-nvdla";
				reg = <0x0 0x15880000 0x0 0x00040000>;
				interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&bpmp TEGRA194_CLK_DLA0_CORE>,
					 <&bpmp TEGRA194_CLK_DLA0_FALCON>;
				clock-names = "nvdla", "nvdla_flcn";
				resets = <&bpmp TEGRA194_RESET_DLA0>;
				reset-names = "nvdla";

				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DLAA>;
				interconnects = <&mc TEGRA194_MEMORY_CLIENT_DLA0RDA &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_DLA0FALRDB &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_DLA0WRA &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_DLA0FALWRB &emc>;
				interconnect-names = "dma-mem", "read-1", "write", "write-1";
				iommus = <&smmu TEGRA194_SID_NVDLA0>;
				dma-coherent;
			};

			nvdla1@158c0000 {
				compatible = "nvidia,tegra194-nvdla";
				reg = <0x0 0x158c0000 0x0 0x00040000>;
				interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&bpmp TEGRA194_CLK_DLA1_CORE>,
					 <&bpmp TEGRA194_CLK_DLA1_FALCON>;
				clock-names = "nvdla", "nvdla_flcn";
				resets = <&bpmp TEGRA194_RESET_DLA1>;
				reset-names = "nvdla";

				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DLAB>;
				interconnects = <&mc TEGRA194_MEMORY_CLIENT_DLA1RDA &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_DLA1FALRDB &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_DLA1WRA &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_DLA1FALWRB &emc>;
				interconnect-names = "dma-mem", "read-1", "write", "write-1";
				iommus = <&smmu TEGRA194_SID_NVDLA1>;
				dma-coherent;
			};

			pva0@16000000 {
				compatible = "nvidia,tegra194-pva";
				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PVAA>;
				reg = <0x0 0x16000000 0x0 0x00800000>,
				      <0x0 0x24f00000 0x0 0x00080000>;
				interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;

				resets = <&bpmp TEGRA194_RESET_PVA0_ALL>;
				reset-names = "nvpva";

				clocks = <&bpmp TEGRA194_CLK_NAFLL_PVA_VPS>,
					 <&bpmp TEGRA194_CLK_NAFLL_PVA_CORE>,
					 <&bpmp TEGRA194_CLK_PVA0_AXI>,
					 <&bpmp TEGRA194_CLK_PVA0_VPS0>,
					 <&bpmp TEGRA194_CLK_PVA0_VPS1>;
				clock-names = "nafll_pva_vps", "nafll_pva_core", "axi", "vps0", "vps1";

                                interconnects = <&mc TEGRA194_MEMORY_CLIENT_PVA0RDA &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_PVA0RDB &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_PVA0RDC &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_PVA0WRA &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_PVA0WRB &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_PVA0WRC &emc>;
				interconnect-names = "dma-mem", "read-b", "read-c", "write-a", "write-b", "write-c";


				iommus = <&smmu TEGRA194_SID_PVA0>;
				dma-coherent;
			};

			pva1@16800000 {
				compatible = "nvidia,tegra194-pva";
				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PVAB>;
				reg = <0x0 0x16800000 0x0 0x00800000>,
				      <0x0 0x24f80000 0x0 0x00080000>;
				interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;

				resets = <&bpmp TEGRA194_RESET_PVA1_ALL>;
				reset-names = "nvpva";

				clocks = <&bpmp TEGRA194_CLK_PVA1_AXI>,
					 <&bpmp TEGRA194_CLK_PVA1_VPS0>,
					 <&bpmp TEGRA194_CLK_PVA1_VPS1>;
				clock-names = "axi", "vps0", "vps1";

                                interconnects = <&mc TEGRA194_MEMORY_CLIENT_PVA1RDA &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_PVA1RDB &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_PVA1RDC &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_PVA1WRA &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_PVA1WRB &emc>,
						<&mc TEGRA194_MEMORY_CLIENT_PVA1WRC &emc>;
				interconnect-names = "dma-mem", "read-b", "read-c", "write-a", "write-b", "write-c";

				iommus = <&smmu TEGRA194_SID_PVA1>;
				dma-coherent;
			};
		};
	};

	fragment@1 {
		target-path = "/";
		__overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;

			cvnas@14000000 {
				compatible = "nvidia,tegra194-cvnas";
				reg = <0x0 0x14000000 0x0 0x20000>, /* CV0_REG0_BASE */
				      <0x0 0x14020000 0x0 0x10000>, /* CV0_SRAM_BASE */
				      <0x0 0x0b240000 0x0 0x10000>; /* HSM_BASE */
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&bpmp TEGRA194_CLK_CVNAS>;
				assigned-clocks = <&bpmp TEGRA194_CLK_CVNAS>;
				assigned-clock-rates = <1356800000>;
				resets = <&bpmp TEGRA194_RESET_CVNAS>,
					 <&bpmp TEGRA194_RESET_CVNAS_FCM>;
				reset-names = "rst", "rst_fcm";
				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_CV>;
				cvsramslice = <4 0x1000>;
				cvsram-reg = <0x0 0x50000000 0x0 0x400000>;
			};
		};
	};
};