# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/platform/tegra/tegra-fsicom.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Device tree binding for NVIDIA Tegra FSICOM

maintainers:
  - Rahul Bedarkar <rabedarkar@nvidia.com>

description: |
   The tegra-fsicom driver provides interface for communication with Functional Safety Island (FSI)

properties:
  compatible:
    enum:
      - nvidia,tegra234-fsicom-client

  mboxes:
    maxItems: 2
    description: |
       Specifies Tx and RX mailboxes for read/write notification.

  mbox-names:
    maxItems: 2
    description: |
       Specifies the name for Tx and Rx mailboxes. Expected Tx mailbox name is "fsi-tx" and Rx mailbox name is "fsi-rx".

  iommus:
    maxItems: 1
    description: |
       A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device.

  iommu-resv-regions:
    maxItems: 1
    description: |
       Pairs of upper and lower start addresses and sizes to reserve memory regions.

  dma-coherent:
    description: |
       Present if dma operations are coherent

required:
  - compatible
  - mboxes
  - mbox-names
  - iommus
  - iommu-resv-regions

additionalProperties: false

examples:
  - |
    #include <dt-bindings/mailbox/tegra186-hsp.h>
    #define TEGRA_SID_NISO1_FSI		0x11U
    #define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8)

    soc {
        fsicom_client {
            compatible = "nvidia,tegra234-fsicom-client";
            mboxes =
                <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(3)>,
                <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(2)>;
            mbox-names = "fsi-tx", "fsi-rx";
            iommus = <&smmu_niso1 TEGRA_SID_NISO1_FSI>;
            iommu-resv-regions = <0x0 0x0 0x0 0xF0000000 0x0 0xF1000000 0xffffffff 0xffffffff>;
            dma-coherent;
        };

     };
...