# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-tegra-slave-byte.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra I2C slave Device Tree binding

maintainers:
  - Laxman Dewangan <ldewangan@nvidia.com>

allOf:
  - $ref: /schemas/i2c/i2c-controller.yaml#

properties:
  compatible:
    enum:
      - nvidia,tegra210-i2c-slave
      - nvidia,tegra-i2c-slave-byte

  reg:
    maxItems: 1
    description: |
       Base address and size of the physical address of I2C controller.

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 2
    description: |
       Two entries, first one is root clock of the controller and second
       one is parent clock of the controller.

  clock-names:
     description: |
        Name of the clock source. The valid names are "div-clk" and "parent".

  resets:
    maxItems: 1
    description: |
       Specifies the reset line.

  reset-names:
    description: |
      Specifies the name of the reset line. Valid name is "i2c".


  clock-frequency:
    minimum: 500
    maximum: 4000000
    default: 100000
    description: frequency of the bus clock in Hz defaults to 100 kHz when not
      specified

  nvidia,hw-instance-id:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Instance ID of the controller.


required:
  - reg
  - compatible
  - clocks
  - clock-names
  - resets
  - reset-names

unevaluatedProperties: false

examples:
  - |
    #define TEGRA234_IRQ_I2C5                29
    #define TEGRA234_CLK_PLLP_OUT0           102U
    #define TEGRA234_CLK_I2C5                305U
    #define TEGRA234_RESET_I2C5              32U

    soc {
       #address-cells = <2>;
       #size-cells = <2>;

       pwr_i2c: i2c@31a0000 {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "nvidia,tegra210-i2c-slave";
            reg = <0x0 0x31a0000 0x0 0x100>;
            nvidia,hw-instance-id = <0x4>;
            interrupts = <0 TEGRA234_IRQ_I2C5 0x04>;
            clock-frequency = <100000>;
            clocks = <&bpmp_clks TEGRA234_CLK_I2C5>,
                     <&bpmp_clks TEGRA234_CLK_PLLP_OUT0>;
            clock-names = "div-clk", "parent";
            resets = <&bpmp_resets TEGRA234_RESET_I2C5>;
            reset-names = "i2c";
        };
    };
...