/* * Copyright (c) 2019-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ /* * This file contains list of SMMU Stream IDs used in Tegra234. */ #ifndef _DT_BINDINGS_MEMORY_TEGRA234_SMMU_STREAMID_H #define _DT_BINDINGS_MEMORY_TEGRA234_SMMU_STREAMID_H /* ********* ISO SMMU STREAM IDs *********** */ #define TEGRA234_SID_ISO_NVDISPLAY 0x1U #define TEGRA_SID_ISO_VI 0x2U #define TEGRA234_SID_ISO_VIFALC 0x3U #define TEGRA234_SID_ISO_VI2 0x4U #define TEGRA234_SID_ISO_VI2FALC 0x5U #define TEGRA234_SID_VI_VM2 0x6U #define TEGRA234_SID_VI2_VM2 0x7U /* ********* NISO0 SMMU STREAM IDs ********** */ #define TEGRA234_SID_AON 0x1U #define TEGRA234_SID_ETR 0x5U #define TEGRA234_SID_NVDISPLAY 0x7U #define TEGRA234_SID_DCE 0x8U #define TEGRA234_SID_PSC 0x9U #define TEGRA234_SID_RCE 0xAU #define TEGRA234_SID_SCE 0xBU #define TEGRA234_SID_UFSHC 0xCU #define TEGRA234_SID_APE_1 0xDU /* The GPC DMA clients. */ #define TEGRA234_SID_GPCDMA_1 0xEU #define TEGRA234_SID_GPCDMA_2 0xFU #define TEGRA234_SID_GPCDMA_3 0x10U #define TEGRA234_SID_GPCDMA_4 0x11U #define TEGRA234_SID_RCE_VM2 0x16U #define TEGRA234_SID_RCE_SERVER 0x17U #define TEGRA234_SID_SMMU_TEST 0x18U /* UFS virtual SIDs for storage clients */ #define TEGRA234_SID_UFS_1 0x19U #define TEGRA234_SID_UFS_2 0x1AU #define TEGRA234_SID_UFS_3 0x1BU #define TEGRA234_SID_UFS_4 0x1CU #define TEGRA234_SID_UFS_5 0x1DU #define TEGRA234_SID_UFS_6 0x1EU #define TEGRA234_SID_NVDLA1 0x23U #define TEGRA234_SID_NVENC 0x24U #define TEGRA234_SID_NVJPG1 0x25U #define TEGRA234_SID_OFA 0x26U /* Reserved streamid corrosponding to NISO1 host1x clients */ #define TEGRA234_SID_NISO1_RESV0 0x27U #define TEGRA234_SID_NISO1_RESV1 0x28U #define TEGRA234_SID_NISO1_RESV2 0x29U #define TEGRA234_SID_NISO1_RESV3 0x2AU #define TEGRA234_SID_NISO1_RESV4 0x2BU #define TEGRA234_SID_NISO1_RESV5 0x2CU #define TEGRA234_SID_NISO1_RESV6 0x2DU #define TEGRA234_SID_NISO1_RESV7 0x2EU #define TEGRA234_SID_NISO1_RESV8 0x2FU #define TEGRA234_SID_NISO1_RESV9 0x30U #define TEGRA234_SID_NISO1_RESV10 0x31U #define TEGRA234_SID_NISO1_RESV11 0x32U #define TEGRA234_SID_NISO1_RESV12 0x33U #define TEGRA234_SID_NISO1_RESV13 0x34U /* Host1x virtualization clients. */ #define TEGRA234_SID_HOST1X_CTX0 0x35U #define TEGRA234_SID_HOST1X_CTX1 0x36U #define TEGRA234_SID_HOST1X_CTX2 0x37U #define TEGRA234_SID_HOST1X_CTX3 0x38U #define TEGRA234_SID_HOST1X_CTX4 0x39U #define TEGRA234_SID_HOST1X_CTX5 0x3AU #define TEGRA234_SID_HOST1X_CTX6 0x3BU #define TEGRA234_SID_HOST1X_CTX7 0x3CU /* Reserved streamid corrosponding to NISO1 host1x clients */ #define TEGRA234_SID_RESV14 0x3DU #define TEGRA234_SID_RESV15 0x3EU #define TEGRA234_SID_RESV16 0x3FU #define TEGRA234_SID_RESV17 0x40U #define TEGRA234_SID_RESV18 0x41U #define TEGRA234_SID_RESV19 0x42U #define TEGRA234_SID_RESV20 0x43U #define TEGRA234_SID_RESV21 0x44U #define TEGRA234_SID_RESV22 0x45U #define TEGRA234_SID_RESV23 0x46U #define TEGRA234_SID_RESV24 0x47U #define TEGRA234_SID_RESV25 0x48U /* MGBE virtualization clients. */ #define TEGRA234_SID_MGBE_VF4 0x4CU #define TEGRA234_SID_MGBE_VF5 0x4DU #define TEGRA234_SID_MGBE_VF6 0x4EU #define TEGRA234_SID_MGBE_VF7 0x4FU #define TEGRA234_SID_MGBE_VF8 0x50U #define TEGRA234_SID_MGBE_VF9 0x51U #define TEGRA234_SID_MGBE_VF10 0x52U #define TEGRA234_SID_MGBE_VF11 0x53U #define TEGRA234_SID_MGBE_VF12 0x54U #define TEGRA234_SID_MGBE_VF13 0x55U #define TEGRA234_SID_MGBE_VF14 0x56U #define TEGRA234_SID_MGBE_VF15 0x57U #define TEGRA234_SID_MGBE_VF16 0x58U #define TEGRA234_SID_MGBE_VF17 0x59U #define TEGRA234_SID_MGBE_VF18 0x5AU #define TEGRA234_SID_MGBE_VF19 0x5BU #define TEGRA234_SID_MGBE_VF20 0x5CU /* FIXME: Hack to support FSI Client on VDK */ #define TEGRA234_SID_VDK_FSI 0x5DU /* Additional APE stream-ids */ #define TEGRA234_SID_APE_2 0x5EU #define TEGRA234_SID_APE_3 0x5FU /* UFS virtual SIDs for storage clients (extra SIDs) */ #define TEGRA234_SID_UFS_7 0x60 #define TEGRA234_SID_UFS_8 0x61 #define TEGRA234_SID_UFS_9 0x62 #define TEGRA234_SID_UFS_10 0x63 #define TEGRA234_SID_UFS_11 0x64 #define TEGRA234_SID_UFS_12 0x65 #define TEGRA234_SID_UFS_13 0x66 #define TEGRA234_SID_UFS_14 0x67 #define TEGRA234_SID_UFS_15 0x68 #define TEGRA234_SID_UFS_16 0x69 #define TEGRA234_SID_UFS_17 0x6A #define TEGRA234_SID_UFS_18 0x6B #define TEGRA234_SID_UFS_19 0x6C #define TEGRA234_SID_UFS_20 0x6D /* Additional SIDs for GPC DMA clients. */ #define TEGRA234_SID_GPCDMA_5 0x6EU #define TEGRA234_SID_GPCDMA_6 0x6FU #define TEGRA234_SID_GPCDMA_7 0x70U #define TEGRA234_SID_GPCDMA_8 0x71U #define TEGRA234_SID_GPCDMA_9 0x72U #define TEGRA234_SID_GPCDMA_10 0x73U #define TEGRA234_SID_GPCDMA_11 0x74U #define TEGRA234_SID_GPCDMA_12 0x75U /* ********* NISO1 SMMU STREAM IDs ********** */ #define TEGRA234_SID_SDMMC1A 0x1U #define TEGRA234_SID_EQOS 0x3U #define TEGRA234_SID_HWMP_PMA 0x4U #define TEGRA234_SID_QSPI0 0xCU #define TEGRA234_SID_QSPI1 0xDU #define TEGRA234_SID_XUSB_HOST 0xEU #define TEGRA234_SID_XUSB_DEV 0xFU #define TEGRA234_SID_NISO1_FSI 0x11U /* PVA virtualization clients. */ #define TEGRA234_SID_PVA0_VM0 0x12U #define TEGRA234_SID_PVA0_VM1 0x13U #define TEGRA234_SID_PVA0_VM2 0x14U #define TEGRA234_SID_PVA0_VM3 0x15U #define TEGRA234_SID_PVA0_VM4 0x16U #define TEGRA234_SID_PVA0_VM5 0x17U #define TEGRA234_SID_PVA0_VM6 0x18U #define TEGRA234_SID_PVA0_VM7 0x19U #define TEGRA234_SID_XUSB_VF0 0x1AU #define TEGRA234_SID_XUSB_VF1 0x1BU #define TEGRA234_SID_XUSB_VF2 0x1CU #define TEGRA234_SID_XUSB_VF3 0x1DU /* EQOS virtual functions */ #define TEGRA234_SID_EQOS_VF1 0x1EU #define TEGRA234_SID_EQOS_VF2 0x1FU #define TEGRA234_SID_EQOS_VF3 0x20U #define TEGRA234_SID_EQOS_VF4 0x21U #define TEGRA234_SID_ISP_VM2 0x22U /* Reserved streamid corrosponding to NISO0 host1x clients */ #define TEGRA234_SID_NISO0_RESV0 0x23U #define TEGRA234_SID_NISO0_RESV1 0x24U #define TEGRA234_SID_NISO0_RESV2 0x25U #define TEGRA234_SID_NISO0_RESV3 0x26U #define TEGRA234_SID_HC 0x27U #define TEGRA234_SID_ISP 0x28U #define TEGRA234_SID_NVDEC 0x29U #define TEGRA234_SID_NVJPG 0x2AU #define TEGRA234_SID_NVDLA0 0x2BU #define TEGRA234_SID_PVA0 0x2CU #define TEGRA234_SID_SES_SE0 0x2DU #define TEGRA234_SID_SES_SE1 0x2EU #define TEGRA234_SID_SES_SE2 0x2FU #define TEGRA234_SID_SEU1_SE0 0x30U #define TEGRA234_SID_SEU1_SE1 0x31U #define TEGRA234_SID_SEU1_SE2 0x32U #define TEGRA234_SID_TSEC 0x33U /* Host1x virtualization clients. */ #define TEGRA234_SID_HOST1X_CTX1 0x36U #define TEGRA234_SID_HOST1X_CTX2 0x37U #define TEGRA234_SID_HOST1X_CTX3 0x38U #define TEGRA234_SID_HOST1X_CTX4 0x39U #define TEGRA234_SID_HOST1X_CTX5 0x3AU #define TEGRA234_SID_HOST1X_CTX6 0x3BU #define TEGRA234_SID_HOST1X_CTX7 0x3CU /* Host1x command buffers */ #define TEGRA234_SID_HC_VM0 0x3DU #define TEGRA234_SID_HC_VM1 0x3EU #define TEGRA234_SID_HC_VM2 0x3FU #define TEGRA234_SID_HC_VM3 0x40U #define TEGRA234_SID_HC_VM4 0x41U #define TEGRA234_SID_HC_VM5 0x42U #define TEGRA234_SID_HC_VM6 0x43U #define TEGRA234_SID_HC_VM7 0x44U /* SE data buffers */ #define TEGRA234_SID_SE_VM0 0x45U #define TEGRA234_SID_SE_VM1 0x46U #define TEGRA234_SID_SE_VM2 0x47U #define TEGRA234_SID_ISPFALC 0x48U #define TEGRA234_SID_NISO1_SMMU_TEST 0x49U #endif /* _DT_BINDINGS_MEMORY_TEGRA234234_SMMU_STREAMID_H */