mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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2852d2419f
Copied sound/tegra-safety-audio source files to nvidia-oot folder Bug 3735757 Change-Id: I8a18ee25a6c33a00e6b28a2e09b6576197a35652 Signed-off-by: pmedawala <pmedawala@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2783432 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Uday Gupta <udayg@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Uday Gupta <udayg@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
239 lines
8.4 KiB
C
239 lines
8.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#ifndef __TEGRA_I2S_REGS_H_
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#define __TEGRA_I2S_REGS_H_
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#define T234_I2S_RX_ENABLE 0x000
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#define T234_I2S_RX_SOFT_RESET 0x004
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#define T234_I2S_RX_STATUS 0x008
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#define T234_I2S_RX_INT_STATUS 0x00c
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#define T234_I2S_RX_INT_SET 0x010
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#define T234_I2S_RX_INT_MASK 0x014
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#define T234_I2S_RX_INT_CLEAR 0x018
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#define T234_I2S_RX_FIFO_CTRL 0x01c
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#define T234_I2S_RX_FIFO_RD_DATA 0x020
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#define T234_I2S_RX_CTRL 0x024
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#define T234_I2S_RX_SLOT_CTRL 0x028
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#define T234_I2S_RX_CLK_TRIM 0x02c
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#define T234_I2S_TX_ENABLE 0x080
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#define T234_I2S_TX_SOFT_RESET 0x084
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#define T234_I2S_TX_STATUS 0x088
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#define T234_I2S_TX_INT_STATUS 0x08c
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#define T234_I2S_TX_INT_SET 0x090
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#define T234_I2S_TX_INT_MASK 0x094
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#define T234_I2S_TX_INT_CLEAR 0x098
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#define T234_I2S_TX_FIFO_CTRL 0x09c
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#define T234_I2S_TX_FIFO_WR_DATA 0x0a0
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#define T234_I2S_TX_START_THRESHOLD 0x0a4
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#define T234_I2S_TX_CTRL 0x0a8
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#define T234_I2S_TX_SLOT_CTRL 0x0ac
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#define T234_I2S_TX_CLK_TRIM 0x0b0
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#define T234_I2S_ENABLE 0x100
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#define T234_I2S_SOFT_RESET 0x104
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#define T234_I2S_CG 0x108
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#define T234_I2S_STATUS 0x10c
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#define T234_I2S_INT_STATUS 0x110
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#define T234_I2S_CTRL 0x114
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#define T234_I2S_TIMING 0x118
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#define T234_I2S_SLOT_CTRL 0x11c
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#define T234_I2S_CLK_TRIM 0x120
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/* Fields in T234_I2S_RX_ENABLE */
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#define T234_I2S_RX_EN_SHIFT 0
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#define T234_I2S_RX_EN (1 << T234_I2S_RX_EN_SHIFT)
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/* Fields in T234_I2S_RX_CTRL */
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#define T234_I2S_RX_CTRL_DATA_OFFSET_SHIFT 8
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#define T234_I2S_RX_CTRL_DATA_OFFSET_MASK \
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(0x7ff << T234_I2S_RX_CTRL_DATA_OFFSET_SHIFT)
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#define T234_I2S_RX_CTRL_MASK_BITS_SHIFT 4
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#define T234_I2S_RX_CTRL_BIT_ORDER_SHIFT 0
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#define T234_I2S_RX_CTRL_BIT_ORDER_MASK \
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(1 << T234_I2S_RX_CTRL_BIT_ORDER_SHIFT)
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#define T234_I2S_RX_CTRL_BIT_ORDER_MSB_FIRST \
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(0 << T234_I2S_RX_CTRL_BIT_ORDER_SHIFT)
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#define T234_I2S_RX_CTRL_BIT_ORDER_LSB_FIRST \
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(1 << T234_I2S_RX_CTRL_BIT_ORDER_SHIFT)
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/* Fields in T234_I2S_TX_ENABLE */
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#define T234_I2S_TX_EN_SHIFT 0
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#define T234_I2S_TX_EN (1 << T234_I2S_TX_EN_SHIFT)
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/* Fields in T234_I2S_TX_CTRL */
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#define T234_I2S_TX_CTRL_DATA_OFFSET_SHIFT 8
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#define T234_I2S_TX_CTRL_DATA_OFFSET_MASK \
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(0x7ff << T234_I2S_TX_CTRL_DATA_OFFSET_SHIFT)
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#define T234_I2S_TX_CTRL_MASK_BITS_SHIFT 4
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#define T234_I2S_TX_CTRL_HIGHZ_CTRL_SHIFT 1
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#define T234_I2S_TX_CTRL_HIGHZ_CTRL_MASK \
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(3 << T234_I2S_TX_CTRL_HIGHZ_CTRL_SHIFT)
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#define T234_I2S_TX_CTRL_HIGHZ_CTRL_NOHIGHZ \
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(0 << T234_I2S_TX_CTRL_HIGHZ_CTRL_SHIFT)
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#define T234_I2S_TX_CTRL_HIGHZ_CTRL_HIGHZ \
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(1 << T234_I2S_TX_CTRL_HIGHZ_CTRL_SHIFT)
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#define T234_I2S_TX_CTRL_HIGHZ_CTRL_HIGHZ_ON_HALF_BIT_CLK \
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(2 << T234_I2S_TX_CTRL_HIGHZ_CTRL_SHIFT)
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#define T234_I2S_TX_CTRL_BIT_ORDER_SHIFT 0
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#define T234_I2S_TX_CTRL_BIT_ORDER_MASK \
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(1 << T234_I2S_TX_CTRL_BIT_ORDER_SHIFT)
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#define T234_I2S_TX_CTRL_BIT_ORDER_MSB_FIRST \
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(0 << T234_I2S_TX_CTRL_BIT_ORDER_SHIFT)
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#define T234_I2S_TX_CTRL_BIT_ORDER_LSB_FIRST \
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(1 << T234_I2S_TX_CTRL_BIT_ORDER_SHIFT)
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/* Fields in T234_I2S_ENABLE */
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#define T234_I2S_EN_SHIFT 0
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#define T234_I2S_EN_MASK (1 << T234_I2S_EN_SHIFT)
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#define T234_I2S_EN (1 << T234_I2S_EN_SHIFT)
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/* Fields in T234_I2S_CTRL */
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#define T234_I2S_CTRL_FSYNC_WIDTH_SHIFT 16
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#define T234_I2S_CTRL_FSYNC_WIDTH_MASK \
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(0xff << T234_I2S_CTRL_FSYNC_WIDTH_SHIFT)
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#define T234_I2S_POS_EDGE 0
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#define T234_I2S_NEG_EDGE 1
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#define T234_I2S_CTRL_EDGE_CTRL_SHIFT 10
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#define T234_I2S_CTRL_EDGE_CTRL_MASK \
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(1 << T234_I2S_CTRL_EDGE_CTRL_SHIFT)
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#define T234_I2S_CTRL_EDGE_CTRL_POS_EDGE \
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(T234_I2S_POS_EDGE << T234_I2S_CTRL_EDGE_CTRL_SHIFT)
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#define T234_I2S_CTRL_EDGE_CTRL_NEG_EDGE \
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(T234_I2S_NEG_EDGE << T234_I2S_CTRL_EDGE_CTRL_SHIFT)
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#define T234_I2S_CTRL_PIPE_MACRO_EN_SHIFT 9
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#define T234_I2S_CTRL_PIPE_MACRO_EN \
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(1 << T234_I2S_CTRL_PIPE_MACRO_EN_SHIFT)
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#define T234_I2S_FRAME_FORMAT_LRCK 0
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#define T234_I2S_FRAME_FORMAT_FSYNC 1
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#define T234_I2S_CTRL_FRAME_FORMAT_SHIFT 6
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#define T234_I2S_CTRL_FRAME_FORMAT_MASK \
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(7 << T234_I2S_CTRL_FRAME_FORMAT_SHIFT)
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#define T234_I2S_CTRL_FRAME_FORMAT_LRCK_MODE \
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(T234_I2S_FRAME_FORMAT_LRCK << T234_I2S_CTRL_FRAME_FORMAT_SHIFT)
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#define T234_I2S_CTRL_FRAME_FORMAT_FSYNC_MODE \
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(T234_I2S_FRAME_FORMAT_FSYNC << T234_I2S_CTRL_FRAME_FORMAT_SHIFT)
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#define T234_I2S_CTRL_MASTER_EN_SHIFT 5
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#define T234_I2S_CTRL_MASTER_EN_MASK \
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(1 << T234_I2S_CTRL_MASTER_EN_SHIFT)
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#define T234_I2S_CTRL_MASTER_EN \
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(1 << T234_I2S_CTRL_MASTER_EN_SHIFT)
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#define T234_I2S_CTRL_SLAVE_EN \
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(1 << T234_I2S_CTRL_MASTER_EN_SHIFT)
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#define T234_I2S_CTRL_LRCK_POLARITY_SHIFT 4
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#define T234_I2S_CTRL_LRCK_POLARITY_MASK \
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(1 << T234_I2S_CTRL_LRCK_POLARITY_SHIFT)
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#define T234_I2S_CTRL_LRCK_POLARITY_LOW \
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(0 << T234_I2S_CTRL_LRCK_POLARITY_SHIFT)
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#define T234_I2S_CTRL_LRCK_POLARITY_HIGH \
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(1 << T234_I2S_CTRL_LRCK_POLARITY_SHIFT)
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#define T234_I2S_CTRL_LPBK_SHIFT 3
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#define T234_I2S_CTRL_LPBK_MASK (1 << T234_I2S_CTRL_LPBK_SHIFT)
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#define T234_I2S_CTRL_LPBK_EN (1 << T234_I2S_CTRL_LPBK_SHIFT)
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#define T234_I2S_BITS_8 1
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#define T234_I2S_BITS_12 2
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#define T234_I2S_BITS_16 3
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#define T234_I2S_BITS_20 4
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#define T234_I2S_BITS_24 5
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#define T234_I2S_BITS_28 6
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#define T234_I2S_BITS_32 7
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#define T234_I2S_CTRL_BIT_SIZE_SHIFT 0
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#define T234_I2S_CTRL_BIT_SIZE_MASK \
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(7 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
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#define T234_I2S_CTRL_BIT_SIZE_8 \
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(T234_I2S_BITS_8 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
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#define T234_I2S_CTRL_BIT_SIZE_12 \
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(T234_I2S_BITS_12 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
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#define T234_I2S_CTRL_BIT_SIZE_16 \
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(T234_I2S_BITS_16 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
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#define T234_I2S_CTRL_BIT_SIZE_20 \
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(T234_I2S_BITS_20 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
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#define T234_I2S_CTRL_BIT_SIZE_24 \
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(T234_I2S_BITS_24 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
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#define T234_I2S_CTRL_BIT_SIZE_28 \
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(T234_I2S_BITS_28 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
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#define T234_I2S_CTRL_BIT_SIZE_32 \
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(T234_I2S_BITS_32 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
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/* Fields in T234_I2S_TIMING */
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#define T234_I2S_TIMING_NON_SYM_EN_SHIFT 12
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#define T234_I2S_TIMING_NON_SYM_EN \
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(1 << T234_I2S_TIMING_NON_SYM_EN_SHIFT)
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#define T234_I2S_TIMING_CHANNEL_BIT_CNT_MASK 0x3ff
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#define T234_I2S_TIMING_CHANNEL_BIT_CNT_SHIFT 0
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/* Fields in T234_I2S_RX_SOFT_RESET */
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#define T234_I2S_RX_SOFT_RESET_SHIFT 0
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#define T234_I2S_RX_SOFT_RESET_MASK \
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(1 << T234_I2S_RX_SOFT_RESET_SHIFT)
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#define T234_I2S_RX_SOFT_RESET_EN \
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(1 << T234_I2S_RX_SOFT_RESET_SHIFT)
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#define T234_I2S_RX_SOFT_RESET_DEFAULT \
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(0 << T234_I2S_RX_SOFT_RESET_SHIFT)
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#define T234_I2S_SCLK_TRIM_SEL_SHIFT 8
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#define T234_I2S_SCLK_TRIM_SEL_MASK 0x1F
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/* Fields in T234_I2S_RX_STATUS */
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#define T234_I2S_RX_STATUS_ENABLED_SHIFT 0
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#define T234_I2S_RX_STATUS_ENABLED \
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(1 << T234_I2S_RX_STATUS_ENABLED_SHIFT)
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#define T234_I2S_RX_STATUS_FIFO_EMPTY_SHIFT 1
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#define T234_I2S_RX_STATUS_FIFO_EMPTY \
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(1 << T234_I2S_RX_STATUS_FIFO_EMPTY_SHIFT)
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#define T234_I2S_RX_STATUS_FIFO_FULL_SHIFT 2
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#define T234_I2S_RX_STATUS_FIFO_FULL \
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(1 << T234_I2S_RX_STATUS_FIFO_FULL_SHIFT)
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#define T234_I2S_RX_STATUS_FIFO_COUNT_SHIFT 8
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#define T234_I2S_RX_STATUS_FIFO_COUNT_MASK \
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(0x7f << T234_I2S_RX_STATUS_FIFO_COUNT_SHIFT)
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/* Fields in T234_I2S_TX_STATUS */
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#define T234_I2S_TX_STATUS_ENABLED_SHIFT 0
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#define T234_I2S_TX_STATUS_ENABLED \
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(1 << T234_I2S_TX_STATUS_ENABLED_SHIFT)
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#define T234_I2S_TX_STATUS_FIFO_EMPTY_SHIFT 1
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#define T234_I2S_TX_STATUS_FIFO_EMPTY \
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(1 << T234_I2S_TX_STATUS_FIFO_EMPTY_SHIFT)
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#define T234_I2S_TX_STATUS_FIFO_FULL_SHIFT 2
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#define T234_I2S_TX_STATUS_FIFO_FULL \
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(1 << T234_I2S_TX_STATUS_FIFO_FULL_SHIFT)
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#define T234_I2S_TX_STATUS_FIFO_COUNT_SHIFT 8
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#define T234_I2S_TX_STATUS_FIFO_COUNT_MASK \
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(0x7f << T234_I2S_TX_STATUS_FIFO_COUNT_SHIFT)
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/* Fields in T234_I2S_TX_SOFT_RESET */
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#define T234_I2S_TX_SOFT_RESET_SHIFT 0
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#define T234_I2S_TX_SOFT_RESET_MASK \
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(1 << T234_I2S_TX_SOFT_RESET_SHIFT)
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#define T234_I2S_TX_SOFT_RESET_EN \
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(1 << T234_I2S_TX_SOFT_RESET_SHIFT)
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#define T234_I2S_TX_SOFT_RESET_DEFAULT \
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(0 << T234_I2S_TX_SOFT_RESET_SHIFT)
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/* Fields in T234_I2S_SLOT_CTRL */
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#define T234_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT 0
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#define T234_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK 0xf
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/* Fields in T234_I2S_TX_SLOT_CTRL */
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#define T234_I2S_TX_SLOT_CTRL_SLOT_ENABLES_SHIFT 0
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#define T234_I2S_TX_SLOT_CTRL_SLOT_ENABLES_MASK 0xffff
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/* Fields in T234_I2S_RX_SLOT_CTRL */
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#define T234_I2S_RX_SLOT_CTRL_SLOT_ENABLES_SHIFT 0
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#define T234_I2S_RX_SLOT_CTRL_SLOT_ENABLES_MASK 0xffff
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#endif /* _TEGRA_I2S_REGS_H_ */
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