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git://nv-tegra.nvidia.com/linux-nv-oot.git
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2e8de96526
Add helper code for booting RISC-V based engines where firmware is located in a carveout. Bug 3778105 Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Change-Id: I36eda4774838fc73098bcf2eff8c3f1983c82465 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2771768 (cherry picked from commit cc6935ec1dc1e6557f5e0a7d53ef9f0c3ff12fb3) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2759060 Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
31 lines
694 B
C
31 lines
694 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, NVIDIA Corporation.
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*/
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#ifndef DRM_TEGRA_RISCV_H
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#define DRM_TEGRA_RISCV_H
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struct tegra_drm_riscv_descriptor {
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u32 manifest_offset;
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u32 code_offset;
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u32 code_size;
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u32 data_offset;
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u32 data_size;
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};
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struct tegra_drm_riscv {
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/* User initializes */
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struct device *dev;
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void __iomem *regs;
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struct tegra_drm_riscv_descriptor bl_desc;
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struct tegra_drm_riscv_descriptor os_desc;
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};
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int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv);
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int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address,
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u32 gscid, const struct tegra_drm_riscv_descriptor *desc);
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#endif
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