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git://nv-tegra.nvidia.com/linux-nv-oot.git
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b20c5f57e3
Use SPDX license GPL-V2.0 format and change Nvidia copyright year to include 2023. Bug 4078035 Change-Id: Icc0060431eb8d9c470a44f4cee50913cc1d8048a Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2890656 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Arun Swain <arswain@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
144 lines
3.0 KiB
C
144 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <dce.h>
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#include <dce-log.h>
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#include <dce-util-common.h>
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#define DCE_MAX_NO_SS 4
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/**
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* ss_set_regs is a 2D array of read-only pointers to a function returning u32.
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*
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* Array of functions that retrun base addresses of shared semaphores set
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* registers in DCE cluster based on the semaphore id and HSP id.
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*/
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__weak u32 (*const ss_set_regs[DCE_MAX_HSP][DCE_MAX_NO_SS])(void) = {
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{
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hsp_ss0_set_r,
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hsp_ss1_set_r,
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hsp_ss2_set_r,
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hsp_ss3_set_r,
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},
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};
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/**
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* ss_clear_regs is a 2D array of read-only pointers to a function
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* returning u32.
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*
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* Array of functions that retrun base addresses of shared semaphores clear
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* registers in DCE cluster based on the semaphore id and HSP id.
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*/
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__weak u32 (*const ss_clear_regs[DCE_MAX_HSP][DCE_MAX_NO_SS])(void) = {
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{
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hsp_ss0_clr_r,
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hsp_ss1_clr_r,
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hsp_ss2_clr_r,
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hsp_ss3_clr_r,
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},
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};
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/**
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* ss_state_regs is a 2D array of read-only pointers to a function
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* returning u32.
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*
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* Array of functions that retrun base addresses of shared semaphores state
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* registers in DCE cluster based on the semaphore id and HSP id.
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*/
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__weak u32 (*const ss_state_regs[DCE_MAX_HSP][DCE_MAX_NO_SS])(void) = {
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{
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hsp_ss0_state_r,
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hsp_ss1_state_r,
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hsp_ss2_state_r,
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hsp_ss3_state_r,
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},
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};
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/**
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* dce_ss_get_state - Get the state of ss_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @id : Shared Semaphore Id.
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*
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* Return : u32
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*/
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u32 dce_ss_get_state(struct tegra_dce *d, u8 id)
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{
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u32 hsp = d->hsp_id;
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return dce_readl(d, ss_state_regs[hsp][id]());
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}
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/**
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* dce_ss_set - Set an u32 value to ss_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @bpos : bit to be set.
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* @id : Shared Semaphore Id.
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*
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* Return : Void
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*/
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void dce_ss_set(struct tegra_dce *d, u8 bpos, u8 id)
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{
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unsigned long val = 0U;
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u32 hsp = d->hsp_id;
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if (hsp >= DCE_MAX_HSP || id >= DCE_MAX_NO_SS) {
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dce_err(d, "Invalid HSP ID:%u OR SS ID:%u", hsp, id);
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return;
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}
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val = dce_ss_get_state(d, id);
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/**
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* Debug info. please remove
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*/
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dce_info(d, "Current Value in SS#%d : %lx", id, val);
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/**
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* TODO :Use DCE_INSERT here.
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*/
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dce_bitmap_set(&val, bpos, 1);
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/**
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* Debug info. please remove
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*/
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dce_info(d, "Value after bitmap operation : %lx", val);
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dce_writel(d, ss_set_regs[hsp][id](), (u32)val);
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/**
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* Debug info. please remove
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*/
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val = dce_ss_get_state(d, id);
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dce_info(d, "Current Value in SS#%d : %lx", id, val);
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}
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/**
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* dce_ss_clear - Clear a bit in ss_#n in the DCE Cluster
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*
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* @d : Pointer to tegra_dce struct.
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* @bpos : bit to be cleared.
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* @id : Shared Semaphore Id.
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*
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* Return : Void
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*/
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void dce_ss_clear(struct tegra_dce *d, u8 bpos, u8 id)
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{
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unsigned long val;
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u32 hsp = d->hsp_id;
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if (hsp >= DCE_MAX_HSP || id >= DCE_MAX_NO_SS) {
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dce_err(d, "Invalid HSP ID:%u OR SS ID:%u", hsp, id);
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return;
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}
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val = dce_ss_get_state(d, id);
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dce_bitmap_set(&val, bpos, 1);
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dce_writel(d, ss_clear_regs[hsp][id](), val);
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}
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