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When EP boot up first and RP in power OFF state, default PERST# input is high due to onboard pull up. When RP is powered ON, it causes a glitch from high to low due to default pinctl settings, it is perceived as PERST# assert by Endpoint. In tegra264_pcie_ep_rst_assert() PRNST# signal is released (set high), this will cause PCIe link up failure. This WAR is initially added for RP reboot case, to handle a scenario where EP function driver still executing core_deinit as part of PERST# assert and mean while RP boot up and ready for link up again. However on Thor it is measured that core_deinit is taking only ~1.4 msec which completes before RP boots. So, it is safe to remove PRNST# release WAR in tegra264_pcie_ep_rst_assert(), this fixes link up failure when RP boot after EP. Bug 4981895 Change-Id: Ie24652a267bf3e3bc740d9c40e5b6d6671429b00 Signed-off-by: Srishti Goel <srgoel@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3345684 (cherry picked from commit 8944b4a4d767a144b7204865d26b4e989ee003b6) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3338072 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>