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After programming the TX Register, it takes 3-4 clock cycles for TX data synchronization to the CEC core domain. The TX_EMPTY interrupt should not be cleared until this data synchronization is complete. Enable CEC HW feature to automatically clears the TX_EMPTY interrupt after TX data synchronization is complete. It takes time for HW to clear the interrupt and TX_EMPTY can still appear high, hence SW needs to poll WR_LOCK until it goes to 0. This will avoid SW to attempt the next TX block during the same TX_EMPTY interrupt. Also read RX_REGISTER based on the buffer occupancy which is indicated by the CEC_RX_BUFFER_STAT_0 register. Bug 4954851 Change-Id: I3ec3792c9ae3b8a00c800c921cf4e4d09369e6b9 Signed-off-by: Ken Chang <kenc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3322519 (cherry picked from commit 94cf6106402dc833dbaa4305c3e1a8f85fd80d0e) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3336992 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Prafull Suryawanshi <prafulls@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>