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ff2271fec3
The code to write the syncpoint channel assignment register incorrectly skips the write if hypervisor registers are not available. The register, however, is within the guest aperture so remove the check and assign syncpoints properly on virtualized systems. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Change-Id: I9a0c8ed42a56c445d392e1ed2b670091be6654fb Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2833919 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Santosh BS <santoshb@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
142 lines
3.2 KiB
C
142 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Tegra host1x Syncpoints
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*
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* Copyright (c) 2010-2013, NVIDIA Corporation.
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*/
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#include <linux/io.h>
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#include "../dev.h"
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#include "../syncpt.h"
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/*
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* Write the current syncpoint value back to hw.
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*/
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static void syncpt_restore(struct host1x_syncpt *sp)
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{
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u32 min = host1x_syncpt_read_min(sp);
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struct host1x *host = sp->host;
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host1x_sync_writel(host, min, HOST1X_SYNC_SYNCPT(sp->id));
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}
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/*
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* Write the current waitbase value back to hw.
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*/
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static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
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{
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#if HOST1X_HW < 7
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struct host1x *host = sp->host;
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host1x_sync_writel(host, sp->base_val,
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HOST1X_SYNC_SYNCPT_BASE(sp->id));
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#endif
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}
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/*
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* Read waitbase value from hw.
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*/
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static void syncpt_read_wait_base(struct host1x_syncpt *sp)
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{
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#if HOST1X_HW < 7
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struct host1x *host = sp->host;
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sp->base_val =
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host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(sp->id));
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#endif
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}
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/*
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* Updates the last value read from hardware.
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*/
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static u32 syncpt_load(struct host1x_syncpt *sp)
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{
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struct host1x *host = sp->host;
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u32 old, live;
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/* Loop in case there's a race writing to min_val */
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do {
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old = host1x_syncpt_read_min(sp);
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live = host1x_sync_readl(host, HOST1X_SYNC_SYNCPT(sp->id));
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} while ((u32)atomic_cmpxchg(&sp->min_val, old, live) != old);
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if (!host1x_syncpt_check_max(sp, live))
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dev_err(host->dev, "%s failed: id=%u, min=%d, max=%d\n",
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__func__, sp->id, host1x_syncpt_read_min(sp),
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host1x_syncpt_read_max(sp));
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return live;
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}
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/*
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* Write a cpu syncpoint increment to the hardware, without touching
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* the cache.
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*/
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static int syncpt_cpu_incr(struct host1x_syncpt *sp)
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{
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struct host1x *host = sp->host;
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u32 reg_offset = sp->id / 32;
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if (!host1x_syncpt_client_managed(sp) &&
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host1x_syncpt_idle(sp))
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return -EINVAL;
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host1x_sync_writel(host, BIT(sp->id % 32),
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HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset));
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wmb();
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return 0;
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}
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/**
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* syncpt_assign_to_channel() - Assign syncpoint to channel
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* @sp: syncpoint
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* @ch: channel
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*
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* On chips with the syncpoint protection feature (Tegra186+), assign @sp to
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* @ch, preventing other channels from incrementing the syncpoints. If @ch is
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* NULL, unassigns the syncpoint.
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*
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* On older chips, do nothing.
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*/
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static void syncpt_assign_to_channel(struct host1x_syncpt *sp,
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struct host1x_channel *ch)
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{
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#if HOST1X_HW >= 6
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struct host1x *host = sp->host;
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host1x_sync_writel(host,
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HOST1X_SYNC_SYNCPT_CH_APP_CH(ch ? ch->id : 0xff),
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HOST1X_SYNC_SYNCPT_CH_APP(sp->id));
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#endif
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}
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/**
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* syncpt_enable_protection() - Enable syncpoint protection
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* @host: host1x instance
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*
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* On chips with the syncpoint protection feature (Tegra186+), enable this
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* feature. On older chips, do nothing.
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*/
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static void syncpt_enable_protection(struct host1x *host)
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{
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#if HOST1X_HW >= 6
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if (!host->hv_regs)
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return;
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host1x_hypervisor_writel(host, HOST1X_HV_SYNCPT_PROT_EN_CH_EN,
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HOST1X_HV_SYNCPT_PROT_EN);
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#endif
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}
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static const struct host1x_syncpt_ops host1x_syncpt_ops = {
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.restore = syncpt_restore,
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.restore_wait_base = syncpt_restore_wait_base,
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.load_wait_base = syncpt_read_wait_base,
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.load = syncpt_load,
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.cpu_incr = syncpt_cpu_incr,
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.assign_to_channel = syncpt_assign_to_channel,
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.enable_protection = syncpt_enable_protection,
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};
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