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0ae09fcdd1
It is unnecessary to spell out license text when we are using SPDX license identifiers. Change-Id: I902e18a413126f4dddb0cbb1fb5c0e0de385d2a1 Signed-off-by: Chris Dragan <kdragan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2892356 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
64 lines
1.3 KiB
C
64 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved. */
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#include "mods_ras.h"
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#include <linux/err.h>
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#include <linux/platform/tegra/carmel_ras.h>
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#include <linux/platform/tegra/tegra18_cpu_map.h>
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/* Encodes requested core/cluster to report
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* ras for. If 0, refers to ccplex
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*/
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static u64 ras_ccplex_config;
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void enable_cpu_core_reporting(u64 config)
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{
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ras_ccplex_config = config;
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}
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void set_err_sel(u64 sel_val)
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{
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u8 core, cluster, ccplex;
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u64 errx;
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ccplex = 0;
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core = ras_ccplex_config >> 1;
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cluster = ras_ccplex_config & 1;
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if (!ras_ccplex_config)
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ccplex = 1;
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if (ccplex) {
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errx = sel_val;
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} else {
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if (!cluster) {
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errx = (tegra18_logical_to_cluster(core) << 5) +
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(tegra18_logical_to_cpu(core) << 4) +
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sel_val;
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} else {
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errx = 512 + (tegra18_logical_to_cluster(core) << 4)
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+ sel_val;
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}
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}
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mods_debug_printk(DEBUG_FUNC, "ERR_SEL is %llu, Core is %u\n",
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errx, core);
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ras_write_errselr(errx);
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}
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void set_err_ctrl(u64 ctrl_val)
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{
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u64 updated_val;
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ras_write_error_control(ctrl_val);
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updated_val = ras_read_error_control();
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mods_debug_printk(DEBUG_ALL, "ERR_CTRL updated value is %llu",
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updated_val);
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}
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u64 get_err_ctrl(void)
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{
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return ras_read_error_control();
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}
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