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119c4f87e2
- Update license of all files in nvadsp that will be used - Remove kernel version checks in the code Bug 4164138 Bug 3682950 Change-Id: Ie1f9ba95c1d46c3dd9bc5614e502b1b444484df6 Signed-off-by: Viswanath L <viswanathl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2980528 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
109 lines
3.4 KiB
C
109 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/**
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* Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __HWMAILBOX_H
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#define __HWMAILBOX_H
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/completion.h>
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#include <linux/spinlock.h>
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/*
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* The interpretation of hwmailbox content is:
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* 31 30 29 0
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* [TAG|TYPE|MESSAGE]
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*/
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#define HWMBOX_TAG_SHIFT 31
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#define HWMBOX_TAG_MASK 0x1
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#define HWMBOX_TAG_INVALID 0
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#define HWMBOX_TAG_VALID 1
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/* Set Invalid TAG */
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#define SET_HWMBOX_TAG_INVALID (HWMBOX_TAG_INVALID << HWMBOX_TAG_SHIFT)
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/* Set Valid TAG */
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#define SET_HWMBOX_TAG_VALID (HWMBOX_TAG_VALID << HWMBOX_TAG_SHIFT)
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/* Get current TAG */
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#define HWMBOX_TAG(val) ((val & HWMBOX_TAG_MASK) << HWMBOX_TAG_SHIFT)
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/*
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* Mailbox can be used for sending short messages and long messages
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*/
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#define HWMBOX_MSG_TYPE_SHIFT 30
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#define HWMBOX_MSG_TYPE_MASK 0x1
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#define HWMBOX_MSG_SMSG 0
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#define HWMBOX_MSG_LMSG 1
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/* Set SMSG type */
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#define SET_HWMBOX_MSG_SMSG (HWMBOX_MSG_SMSG << HWMBOX_MSG_TYPE_SHIFT)
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/* Set LMSG type */
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#define SET_HWMBOX_MSG_LMSG (HWMBOX_MSG_LMSG << HWMBOX_MSG_TYPE_SHIFT)
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/* Get MSG type */
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#define HWMBOX_MSG_TYPE(val) \
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((val >> HWMBOX_MSG_TYPE_SHIFT) & HWMBOX_MSG_TYPE_MASK)
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/* Check if SMSG */
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#define IS_HWMBOX_MSG_SMSG(val) \
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(!((val >> HWMBOX_MSG_TYPE_SHIFT) & HWMBOX_MSG_TYPE_MASK))
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/* Check if LMSG */
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#define IS_HWMBOX_MSG_LMSG(val) \
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((val >> HWMBOX_MSG_TYPE_SHIFT) & HWMBOX_MSG_TYPE_MASK)
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/*
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* The format for a short message is:
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* 31 30 29 20 19 0
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* [TAG|TYPE|MBOX ID|SHORT MESSAGE]
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* 1b 1b 10bits 20bits
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*/
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#define HWMBOX_SMSG_SHIFT 0
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#define HWMBOX_SMSG_MASK 0x3FFFFFFF
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#define HWMBOX_SMSG(val) ((val >> HWMBOX_SMSG_SHIFT) & HWMBOX_SMSG_MASK)
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#define HWMBOX_SMSG_MID_SHIFT 20
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#define HWMBOX_SMSG_MID_MASK 0x3FF
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#define HWMBOX_SMSG_MID(val) \
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((val >> HWMBOX_SMSG_MID_SHIFT) & HWMBOX_SMSG_MID_MASK)
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#define HWMBOX_SMSG_MSG_SHIFT 0
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#define HWMBOX_SMSG_MSG_MASK 0xFFFFF
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#define HWMBOX_SMSG_MSG(val) \
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((val >> HWMBOX_SMSG_MSG_SHIFT) & HWMBOX_SMSG_MSG_MASK)
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/* Set mailbox id for a short message */
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#define SET_HWMBOX_SMSG_MID(val) \
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((val & HWMBOX_SMSG_MID_MASK) << HWMBOX_SMSG_MID_SHIFT)
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/* Set msg value in a short message */
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#define SET_HWMBOX_SMSG_MSG(val) \
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((val & HWMBOX_SMSG_MSG_MASK) << HWMBOX_SMSG_MSG_SHIFT)
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/* Prepare a small message with mailbox id and data */
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#define PREPARE_HWMBOX_SMSG(mid, data) (SET_HWMBOX_TAG_VALID | \
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SET_HWMBOX_MSG_SMSG | \
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SET_HWMBOX_SMSG_MID(mid) | \
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SET_HWMBOX_SMSG_MSG(data))
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/* Prepare empty mailbox value */
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#define PREPARE_HWMBOX_EMPTY_MSG() (HWMBOX_TAG_INVALID | 0x0)
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/*
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* Queue size must be power of 2 as '&' op
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* is being used to manage circular queues
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*/
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#define HWMBOX_QUEUE_SIZE 1024
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#define HWMBOX_QUEUE_SIZE_MASK (HWMBOX_QUEUE_SIZE - 1)
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struct hwmbox_queue {
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uint32_t array[HWMBOX_QUEUE_SIZE];
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uint16_t head;
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uint16_t tail;
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uint16_t count;
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struct completion comp;
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spinlock_t lock;
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};
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u32 hwmb_reg_idx(void);
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u32 hwmbox_readl(u32 reg);
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void hwmbox_writel(u32 val, u32 reg);
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int nvadsp_hwmbox_init(struct platform_device *);
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status_t nvadsp_hwmbox_send_data(uint16_t, uint32_t, uint32_t);
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void dump_mailbox_regs(void);
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int nvadsp_setup_hwmbox_interrupts(struct platform_device *pdev);
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void nvadsp_free_hwmbox_interrupts(struct platform_device *pdev);
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#endif /* __HWMAILBOX_H */
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