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1f56aa1d73
PCI supports IO BAR with 32-bit address, however XAL HW module provide a way to use 64-bit MMIO address as a CPU address and a 32-bit PCI address for IO BAR. Program 64-bit MMIO address in XAL registers, when sending the TLP over the bus, XAL truncates it to 32-bit address. Bug 4883004 Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Change-Id: Idf2fdfa9d345ae7d0630d4ab9b1074422a9f68f4 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3256977 Reviewed-by: Ankit Patel (SW-TEGRA) <anpatel@nvidia.com> Tested-by: Ankit Patel (SW-TEGRA) <anpatel@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>