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527743a5c3
Actmon is a hardware block that can be used to track the activity of certain hardware units. It can boost EMC clock depending on the memory traffic among various client. It is called central actmon as it monitors central activity for example MC activity. Add central activity monitor driver. Bug 3625675 Change-Id: I1a5918e7d84bc247f694f53f965c28888b773c91 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2705395 GVS: Gerrit_Virtual_Submit
74 lines
2.3 KiB
C
74 lines
2.3 KiB
C
/*
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* Copyright (c) 2020-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _DT_BINDINGS_TEGRA_ICC_ID_H
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#define _DT_BINDINGS_TEGRA_ICC_ID_H
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/* ICC master node */
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#define TEGRA_ICC_PRIMARY 0
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#define TEGRA_ICC_DEBUG 1
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#define TEGRA_ICC_CPU_CLUSTER0 2
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#define TEGRA_ICC_CPU_CLUSTER1 3
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#define TEGRA_ICC_CPU_CLUSTER2 4
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#define TEGRA_ICC_GPU 5
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#define TEGRA_ICC_CACTMON 6
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#define TEGRA_ICC_DISPLAY 7
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#define TEGRA_ICC_VI 8
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#define TEGRA_ICC_EQOS 9
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#define TEGRA_ICC_PCIE_0 10
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#define TEGRA_ICC_PCIE_1 11
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#define TEGRA_ICC_PCIE_2 12
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#define TEGRA_ICC_PCIE_3 13
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#define TEGRA_ICC_PCIE_4 14
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#define TEGRA_ICC_PCIE_5 15
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#define TEGRA_ICC_PCIE_6 16
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#define TEGRA_ICC_PCIE_7 17
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#define TEGRA_ICC_PCIE_8 18
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#define TEGRA_ICC_PCIE_9 19
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#define TEGRA_ICC_PCIE_10 20
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#define TEGRA_ICC_DLA_0 21
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#define TEGRA_ICC_DLA_1 22
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#define TEGRA_ICC_SDMMC_1 23
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#define TEGRA_ICC_SDMMC_2 24
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#define TEGRA_ICC_SDMMC_3 25
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#define TEGRA_ICC_SDMMC_4 26
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#define TEGRA_ICC_NVDEC 27
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#define TEGRA_ICC_NVENC 28
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#define TEGRA_ICC_NVJPG_0 29
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#define TEGRA_ICC_NVJPG_1 30
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#define TEGRA_ICC_OFAA 31
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#define TEGRA_ICC_XUSB_HOST 32
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#define TEGRA_ICC_XUSB_DEV 33
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#define TEGRA_ICC_TSEC 34
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#define TEGRA_ICC_VIC 35
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#define TEGRA_ICC_APE 36
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#define TEGRA_ICC_APEDMA 37
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#define TEGRA_ICC_SE 38
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#define TEGRA_ICC_ISP 39
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#define TEGRA_ICC_HDA 40
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#define TEGRA_ICC_VIFAL 41
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#define TEGRA_ICC_VI2FAL 42
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#define TEGRA_ICC_VI2 43
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#define TEGRA_ICC_RCE 44
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#define TEGRA_ICC_PVA 45
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#define TEGRA_ICC_NVPMODEL 46
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/* remove later */
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#define NV_NVDISPLAYR2MC_SR_ID TEGRA_ICC_DISPLAY
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#define TEGRA_ICC_MASTER TEGRA_ICC_PRIMARY
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#endif /* _DT_BINDINGS_TEGRA_ICC_ID_H */
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