mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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b32bd99824
This performs following trivial cleanup:
- Remove explicit THIS_MODULE assignment in platform_driver struct.
- Remove DRV_NAME macro and assign the name directly in platform_driver
struct.
- Add SPDX-License-Identifier to header files
- Sort header file inclusions
Bug 200698314
Change-Id: Ic1e2166b6a8257cd3b462cc8b2a9719e25c7bbb8
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
103 lines
4.3 KiB
C
103 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra186_arad.h - Definitions for Tegra186 ARAD driver
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*
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* Copyright (c) 2015-2021, NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA186_ARAD_H__
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#define __TEGRA186_ARAD_H__
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#define TEGRA186_ARAD_LANE_STRIDE 0x38
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#define TEGRA186_ARAD_LANE_START 0x40
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#define TEGRA186_ARAD_LANE_MAX 6
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#define TEGRA186_ARAD_LANE_LIMIT (TEGRA186_ARAD_LANE_START + (TEGRA186_ARAD_LANE_MAX * TEGRA186_ARAD_LANE_STRIDE))
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#define TEGRA186_ARAD_LANE_ENABLE 0x0
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#define TEGRA186_ARAD_LANE_STATUS 0x4
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#define TEGRA186_ARAD_LANE_SOFT_RESET 0x8
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#define TEGRA186_ARAD_LANE_INT_STATUS 0xc
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#define TEGRA186_ARAD_LANE_INT_MASK 0x10
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#define TEGRA186_ARAD_LANE_INT_SET 0x14
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#define TEGRA186_ARAD_LANE_INT_CLEAR 0x18
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#define TEGRA186_ARAD_LANE_INT_RATIO_CHANGE_MASK (0x3f<<16)
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#define TEGRA186_ARAD_LANE_INT_LOCK_CHANGE_MASK 0x3f
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#define TEGRA186_ARAD_LANE_INT_RATIO_CHANGE_SHIFT 16
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#define TEGRA186_ARAD_LANE_INT_LOCK_CHANGE_SHIFT 0
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#define TEGRA186_ARAD_GLOBAL_SOFT_RESET 0x1c
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#define TEGRA186_ARAD_CG 0x20
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#define TEGRA186_ARAD_STATUS 0x24
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#define TEGRA186_ARAD_SEND_RATIO 0x28
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#define TEGRA186_ARAD_CYA_GLOBAL 0x2c
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#define TEGRA186_ARAD_TX_CIF_CTRL 0x190
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#define TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL 0x40
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#define TEGRA186_ARAD_LANE1_NUMERATOR_PRESCALAR 0x44
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#define TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL 0x48
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#define TEGRA186_ARAD_LANE1_DENOMINATOR_PRESCALAR 0x4c
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#define TEGRA186_ARAD_LANE1_RATIO_INTEGER_PART 0x50
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#define TEGRA186_ARAD_LANE1_RATIO_FRACTIONAL_PART 0x54
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#define TEGRA186_ARAD_LANE1_PERIOD_COUNT 0x58
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#define TEGRA186_ARAD_LANE1_SERVO_LOOP_CONFIG 0x5c
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#define TEGRA186_ARAD_LANE1_LOCK_UNLOCK_DETECTOR_CONFIG 0x60
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#define TEGRA186_ARAD_LANE1_ERROR_LOCK_THRESHOLD 0x64
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#define TEGRA186_ARAD_LANE1_ERROR_UNLOCK_THRESHOLD 0x68
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#define TEGRA186_ARAD_LANE1_RATIO_CALCULATOR_CONFIG 0x6c
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#define TEGRA186_ARAD_LANE1_CYA 0x70
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#define TEGRA186_ARAD_LANE2_NUMERATOR_MUX_SEL 0x78
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#define TEGRA186_ARAD_LANE2_DENOMINATOR_MUX_SEL 0x80
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#define TEGRA186_ARAD_LANE3_NUMERATOR_MUX_SEL 0xb0
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#define TEGRA186_ARAD_LANE3_DENOMINATOR_MUX_SEL 0xb8
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#define TEGRA186_ARAD_LANE4_NUMERATOR_MUX_SEL 0xe8
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#define TEGRA186_ARAD_LANE4_DENOMINATOR_MUX_SEL 0xf0
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#define TEGRA186_ARAD_LANE5_NUMERATOR_MUX_SEL 0x120
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#define TEGRA186_ARAD_LANE5_DENOMINATOR_MUX_SEL 0x128
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#define TEGRA186_ARAD_LANE6_NUMERATOR_MUX_SEL 0x158
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#define TEGRA186_ARAD_LANE6_DENOMINATOR_MUX_SEL 0x160
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#define TEGRA186_ARAD_LANE2_RATIO_INTEGER_PART 0x88
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#define TEGRA186_ARAD_LANE2_RATIO_FRACTIONAL_PART 0x8c
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#define TEGRA186_ARAD_LANE3_RATIO_INTEGER_PART 0xc0
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#define TEGRA186_ARAD_LANE3_RATIO_FRACTIONAL_PART 0xc4
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#define TEGRA186_ARAD_LANE4_RATIO_INTEGER_PART 0xf8
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#define TEGRA186_ARAD_LANE4_RATIO_FRACTIONAL_PART 0xfc
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#define TEGRA186_ARAD_LANE5_RATIO_INTEGER_PART 0x130
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#define TEGRA186_ARAD_LANE5_RATIO_FRACTIONAL_PART 0x134
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#define TEGRA186_ARAD_LANE6_RATIO_INTEGER_PART 0x168
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#define TEGRA186_ARAD_LANE6_RATIO_FRACTIONAL_PART 0x16c
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#define TEGRA186_ARAD_LANE_ENABLE_SHIFT 0
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#define TEGRA186_ARAD_LANE_ENABLE_MASK (0x3f << TEGRA186_ARAD_LANE_ENABLE_SHIFT)
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#define TEGRA186_ARAD_LANE1_ENABLE_SHIFT 0
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#define TEGRA186_ARAD_LANE1_ENABLE_MASK (0x1 << TEGRA186_ARAD_LANE1_ENABLE_SHIFT)
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#define TEGRA186_ARAD_LANE2_ENABLE_SHIFT 1
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#define TEGRA186_ARAD_LANE2_ENABLE_MASK (0x1 << TEGRA186_ARAD_LANE2_ENABLE_SHIFT)
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#define TEGRA186_ARAD_LANE3_ENABLE_SHIFT 2
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#define TEGRA186_ARAD_LANE3_ENABLE_MASK (0x1 << TEGRA186_ARAD_LANE3_ENABLE_SHIFT)
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#define TEGRA186_ARAD_LANE4_ENABLE_SHIFT 3
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#define TEGRA186_ARAD_LANE4_ENABLE_MASK (0x1 << TEGRA186_ARAD_LANE4_ENABLE_SHIFT)
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#define TEGRA186_ARAD_LANE5_ENABLE_SHIFT 4
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#define TEGRA186_ARAD_LANE5_ENABLE_MASK (0x1 << TEGRA186_ARAD_LANE5_ENABLE_SHIFT)
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#define TEGRA186_ARAD_LANE6_ENABLE_SHIFT 5
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#define TEGRA186_ARAD_LANE6_ENABLE_MASK (0x1 << TEGRA186_ARAD_LANE6_ENABLE_SHIFT)
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#define TEGRA186_ARAD_LANE_LOCK_STATUS_SHIFT 16
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#define TEGRA186_ARAD_LANE_ENABLED_STATUS_SHIFT 0
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#define TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK 0xFFFFFFFF
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#define TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK 0xFFFFFFFF
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struct tegra186_arad {
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struct regmap *regmap;
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#if defined CONFIG_SND_SOC_TEGRA186_ARAD_WAR
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unsigned int int_status;
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spinlock_t status_lock;
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#endif
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};
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void tegra186_arad_send_ratio(void);
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#endif
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