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2893067ed3
Add dma-mask parsing in device tree for eqos driver if IOMMU is enabled. This will allow memory allocations from the specified address and downwards, while device can reach every part of physical memory through the IOMMU. dma-mask will be remain default 32-bit mask if no IOMMU is present since now DMA mask represents a fundamental limit of the device. Bug 200458098 Change-Id: I6eef70f97dba5807d6483cbd76e474d321debe75 Signed-off-by: Narayan Reddy <narayanr@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2096023 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
139 lines
3.9 KiB
C
139 lines
3.9 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef ETHER_LINUX_H
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#define ETHER_LINUX_H
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#include <linux/platform_device.h>
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#include <linux/etherdevice.h>
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#include <linux/interrupt.h>
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#include <linux/of_gpio.h>
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#include <linux/of_mdio.h>
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#include <linux/if_vlan.h>
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#include <linux/of_net.h>
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#include <linux/module.h>
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#include <linux/reset.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <osi_core.h>
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#include <osi_dma.h>
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#define ETHER_MAX_IRQS 4
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#define ETHER_IRQ_MAX_IDX 8
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#define ETHER_IRQ_NAME_SZ 32
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/**
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* struct ether_tx_napi - DMA Transmit Channel NAPI
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* @chan: Transmit channel number
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* @pdata: OSD private data
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* @napi: NAPI instance associated with transmit channel
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*/
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struct ether_tx_napi {
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unsigned int chan;
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struct ether_priv_data *pdata;
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struct napi_struct napi;
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};
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/**
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* struct ether_rx_napi - DMA Receive Channel NAPI
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* @chan: Receive channel number
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* @pdata: OSD Private data
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* @napi: NAPI instance associated with receive channel
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*/
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struct ether_rx_napi {
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unsigned int chan;
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struct ether_priv_data *pdata;
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struct napi_struct napi;
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};
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/**
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* struct ether_priv_data - Ethernet driver private data
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* @osi_core: OSI core private data
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* @osi_dma: OSI DMA private data
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* @hwfeat: HW supported feature list
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* @tx_napi: Array of DMA Transmit channel NAPI
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* @rx_napi: Array of DMA Receive channel NAPI
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* @ndev: Network device associated with driver
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* @dev: Base device associated with driver
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* @mac_rst: Reset for the MAC
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* @pllrefe_clk: PLLREFE clock
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* @axi_clk: Clock from AXI
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* @axi_cbb_clk: Clock from AXI CBB
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* @rx_clk: Receive clock (which will be driven from the PHY)
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* @ptp_ref_clk: PTP reference clock from AXI
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* @tx_clk: Transmit clock
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* @phy_node: Pointer to PHY device tree node
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* @mdio_node: Pointer to MDIO device tree node
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* @mii: Pointer to MII bus instance
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* @phydev: Pointer to the PHY device
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* @interface: Interface type assciated with MAC (SGMII/RGMII/...)
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* this information will be provided with phy-mode DT
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* entry
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* @oldlink: Previous detected link
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* @speed: PHY link speed
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* @oldduplex: Previous detected mode
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* @phy_reset: Reset for PHY
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* @rx_irq_alloc_mask: Tx IRQ alloc mask
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* @tx_irq_alloc_mask: Rx IRQ alloc mask
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* @common_irq: Common IRQ number for MAC
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* @tx_irqs: Array of DMA Transmit channel IRQ numbers
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* @rx_irqs: Array of DMA Receive channel IRQ numbers
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* dma_mask: memory allocation mask
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*/
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struct ether_priv_data {
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struct osi_core_priv_data *osi_core;
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struct osi_dma_priv_data *osi_dma;
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struct osi_hw_features hw_feat;
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struct ether_tx_napi *tx_napi[OSI_EQOS_MAX_NUM_CHANS];
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struct ether_rx_napi *rx_napi[OSI_EQOS_MAX_NUM_CHANS];
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struct net_device *ndev;
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struct device *dev;
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struct reset_control *mac_rst;
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struct clk *pllrefe_clk;
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struct clk *axi_clk;
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struct clk *axi_cbb_clk;
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struct clk *rx_clk;
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struct clk *ptp_ref_clk;
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struct clk *tx_clk;
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struct device_node *phy_node;
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struct device_node *mdio_node;
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struct mii_bus *mii;
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struct phy_device *phydev;
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int interface;
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unsigned int oldlink;
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int speed;
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int oldduplex;
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int phy_reset;
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unsigned int rx_irq_alloc_mask;
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unsigned int tx_irq_alloc_mask;
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int common_irq;
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int tx_irqs[ETHER_MAX_IRQS];
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int rx_irqs[ETHER_MAX_IRQS];
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unsigned long long dma_mask;
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};
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void ether_set_ethtool_ops(struct net_device *ndev);
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#endif /* ETHER_LINUX_H */
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