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git://nv-tegra.nvidia.com/linux-nv-oot.git
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975ca77f46
Adding support in existing mttcan driver to control T264 FSI CAN controllers from CCPLEX whether FSI firmware is loaded on system or not. FSI CAN clocks will be enabled by FSI crystal clock upon boot. SW does not need to enable or control clocks. CCPLEX cannot control FSI controller resets, reset can be handled during boot, thus disabled clocks and reset for T264 SOC. Bug 4317516 Change-Id: I8e6b20640c8763ebc0a9d9192e3212a49902f9b4 Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*/
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#ifndef _M_TTCAN_LINUX_H
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#define _M_TTCAN_LINUX_H
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#include <linux/list.h>
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#include <linux/vmalloc.h>
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#include <linux/slab.h>
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#include <linux/kernel.h>
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#include <linux/netdevice.h>
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#include <linux/can/dev.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/if_arp.h>
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#include <linux/if_ether.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/net_tstamp.h>
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#include <linux/spinlock.h>
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#include <linux/clocksource.h>
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#if defined(CONFIG_TEGRA_PROD_LEGACY)
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#include <linux/tegra_prod.h>
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#endif
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#include <linux/platform/tegra/ptp-notifier.h>
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#include <linux/mailbox_client.h>
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#ifdef CONFIG_CLK_SRC_TEGRA18_US_TIMER
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#include <linux/tegra-us-timer.h>
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#endif
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#include <asm/io.h>
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#include "m_ttcan_ivc.h"
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#define MTTCAN_RX_FIFO_INTR (0xFF)
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#define MTTCAN_RX_HP_INTR (0x1 << 8)
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#define MTTCAN_TX_EV_FIFO_INTR (0xF << 12)
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#define MTTCAN_ERR_INTR (0x1FF9 << 17)
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#define MTTCAN_BUS_OFF (1 << 25)
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#define MTTCAN_ERR_WARN (1 << 24)
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#define MTTCAN_ERR_PASS (1 << 23)
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#define MTT_CAN_NAPI_WEIGHT 64
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#define MTT_CAN_TX_OBJ_NUM 32
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#define MTT_CAN_MAX_MRAM_ELEMS 9
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#define MTT_MAX_TX_CONF 4
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#define MTT_MAX_RX_CONF 3
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#define MTTCAN_POLL_TIME 50
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#define MTTCAN_HWTS_ROLLOVER 250
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/* block period in ms */
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#define TX_BLOCK_PERIOD 200
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#define TSC_REF_CLK_RATE 31250000
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#define MTTCAN_TSC_SIZE 16U
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#define MTTCAN_TSC_MASK 0xFFFFULL
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#define TSC_REF_CLK_SHIFT 9U
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struct tegra_mttcan_soc_info {
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bool enable_clocks;
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bool set_can_core_clk;
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unsigned long can_core_clk_rate;
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unsigned long can_clk_rate;
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bool use_external_timer;
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bool control_reset;
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};
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struct can_gpio {
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struct gpio_desc *gpio;
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int active_low;
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};
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struct mttcan_priv {
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struct can_priv can;
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struct ttcan_controller *ttcan;
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const struct tegra_mttcan_soc_info *sinfo;
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struct delayed_work can_work;
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struct delayed_work drv_restart_work;
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struct napi_struct napi;
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struct net_device *dev;
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struct device *device;
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struct clk *can_clk, *host_clk, *core_clk;
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struct can_gpio gpio_can_en;
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struct can_gpio gpio_can_stb;
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struct timer_list timer;
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struct cyclecounter cc;
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struct timecounter tc;
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struct hwtstamp_config hwtstamp_config;
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struct mbox_client cl;
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struct completion xfer_completion;
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struct mbox_chan *mbox;
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raw_spinlock_t tc_lock; /* lock to protect timecounter infra */
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spinlock_t tslock; /* lock to protect ioctl */
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spinlock_t tx_lock; /* lock to protect transmit path */
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void __iomem *regs;
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void __iomem *mres;
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void *std_shadow;
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void *xtd_shadow;
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void *tmc_shadow;
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u32 gfc_reg;
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u32 xidam_reg;
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u32 irq_flags;
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u32 irq_ttflags;
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u32 irqstatus;
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u32 tt_irqstatus;
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u32 instance;
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int tt_intrs;
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int tt_param[2];
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u32 mram_param[MTT_CAN_MAX_MRAM_ELEMS];
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u32 tx_conf[MTT_MAX_TX_CONF]; /*<txb, txq, txq_mode, txb_dsize>*/
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u32 rx_conf[MTT_MAX_RX_CONF]; /*<rxb_dsize, rxq0_dsize, rxq1_dsize>*/
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bool poll;
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bool hwts_rx_en;
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u32 resp;
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};
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int mttcan_create_sys_files(struct device *dev);
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void mttcan_delete_sys_files(struct device *dev);
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#endif
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