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linux-nv-oot/drivers/net/can/mttcan/include/m_ttcan_regdef.h
Laxman Dewangan 9a65689ba2 mttcan: tegra: Add new prod setting support 
Add new prod setting support which is the
property based on device tree. The prod
setting of each register field are new property
in DT and prod configurations are configured
via these new properties.

Bug 4097475

Change-Id: I86adc7b72a28802d73fee8a085db2bccf0d6d1cc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2996771
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-10-14 05:56:30 -07:00

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32 KiB
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*/
#ifndef M_TTCAN_REGDEF_H_
#define M_TTCAN_REGDEF_H_
#define ADR_MTTCAN_CREL 0x00
#define ADR_MTTCAN_ENDN 0x004
#define DEF_MTTCAN_ENDN 0x87654321
#define ADR_MTTCAN_DBTP 0x00C
#define DEF_MTTCAN_DBTP 0x00000A33
#define MTTCAN_DBTP_MSK 0x009F1FFF
#define MTTCAN_CORE_DBTP_TDC_FIELD_START 23
#define MTTCAN_CORE_DBTP_TDC_FIELD_WIDTH 1
#define ADR_MTTCAN_TEST 0x010
#define DEF_MTTCAN_TEST 0x00000080
#define MTTCAN_TEST_MSK 0xFFFF8000
#define ADR_MTTCAN_RWD 0x014
#define DEF_MTTCAN_RWD 0x00000000
#define ADR_MTTCAN_CCCR 0x018
#define DEF_MTTCAN_CCCR 0x00000001
#define MTTCAN_CCCR_MSK 0X0000F3FF
#define ADR_MTTCAN_NBTP 0x01C
#define DEF_MTTCAN_NBTP 0x00000A33
#define MTTCAN_NBTP_MSK 0x03FF3FFF
#define ADR_MTTCAN_TSCC 0x020
#define DEF_MTTCAN_TSCC 0x00000000
#define ADR_MTTCAN_TSCV 0x024
#define DEF_MTTCAN_TSCV 0x00000000
#define ADR_MTTCAN_TOCC 0x028
#define DEF_MTTCAN_TOCC 0xFFFF0000
#define ADR_MTTCAN_TOCV 0x02C
#define DEF_MTTCAN_TOCV 0x0000FFFF
#define ADR_MTTCAN_ECR 0x040
#define DEF_MTTCAN_ECR 0x00000000
#define ADR_MTTCAN_PSR 0x044
#define DEF_MTTCAN_PSR 0x00000707
#define ADR_MTTCAN_TDCR 0x048
#define DEF_MTTCAN_TDCR 0x00000000
#define MTTCAN_TDCR_MSK 0x00007F7F
#define MTTCAN_CORE_TDCR_TDCO_FIELD_START 8
#define MTTCAN_CORE_TDCR_TDCO_FIELD_WIDTH 7
#define ADR_MTTCAN_IR 0x050
#define DEF_MTTCAN_IR 0x00000000
#define ADR_MTTCAN_IE 0x054
#define DEF_MTTCAN_IE 0x00000000
#define ADR_MTTCAN_ILS 0x058
#define DEF_MTTCAN_ILS 0x00000000
#define ADR_MTTCAN_ILE 0x05C
#define DEF_MTTCAN_ILE 0x00000000
#define ADR_MTTCAN_GFC 0x080
#define DEF_MTTCAN_GFC 0x00000000
#define MTTCAN_GFC_MSK 0x0000003F
#define ADR_MTTCAN_SIDFC 0x084
#define DEF_MTTCAN_SIDFC 0x00000000
#define ADR_MTTCAN_XIDFC 0x088
#define DEF_MTTCAN_XIDFC 0x00000000
#define ADR_MTTCAN_XIDAM 0x090
#define DEF_MTTCAN_XIDAM 0x1FFFFFFF
#define MTTCAN_XIDAM_MSK 0x1FFFFFFF
#define ADR_MTTCAN_HPMS 0x094
#define DEF_MTTCAN_HPMS 0x00000000
#define ADR_MTTCAN_NDAT1 0x098
#define DEF_MTTCAN_NDAT1 0x00000000
#define ADR_MTTCAN_NDAT2 0x09C
#define DEF_MTTCAN_NDAT2 0x00000000
#define ADR_MTTCAN_RXF0C 0x0A0
#define DEF_MTTCAN_RXF0C 0x00000000
#define ADR_MTTCAN_RXF0S 0x0A4
#define DEF_MTTCAN_RXF0S 0x00000000
#define ADR_MTTCAN_RXF0A 0x0A8
#define DEF_MTTCAN_RXF0A 0x00000000
#define ADR_MTTCAN_RXBC 0x0AC
#define DEF_MTTCAN_RXBC 0x00000000
#define ADR_MTTCAN_RXF1C 0x0B0
#define DEF_MTTCAN_RXF1C 0x00000000
#define ADR_MTTCAN_RXF1S 0x0B4
#define DEF_MTTCAN_RXF1S 0x00000000
#define ADR_MTTCAN_RXF1A 0x0B8
#define DEF_MTTCAN_RXF1A 0x00000000
#define ADR_MTTCAN_RXESC 0x0BC
#define DEF_MTTCAN_RXESC 0x00000000
#define ADR_MTTCAN_TXBC 0x0C0
#define DEF_MTTCAN_TXBC 0x00000000
#define MTTCAN_TXBC_MSK 0x7F3FFFFC
#define ADR_MTTCAN_TXFQS 0x0C4
#define DEF_MTTCAN_TXFQS 0x00000000
#define ADR_MTTCAN_TXESC 0x0C8
#define DEF_MTTCAN_TXESC 0x00000000
#define MTTCAN_TXESC_MSK 0x00000007
#define ADR_MTTCAN_TXBRP 0x0CC
#define DEF_MTTCAN_TXBRP 0x00000000
#define ADR_MTTCAN_TXBAR 0x0D0
#define DEF_MTTCAN_TXBAR 0x00000000
#define ADR_MTTCAN_TXBCR 0x0D4
#define DEF_MTTCAN_TXBCR 0x00000000
#define ADR_MTTCAN_TXBTO 0x0D8
#define DEF_MTTCAN_TXBTO 0x00000000
#define ADR_MTTCAN_TXBCF 0x0DC
#define DEF_MTTCAN_TXBCF 0x00000000
#define ADR_MTTCAN_TXBTIE 0x0E0
#define DEF_MTTCAN_TXBTIE 0x00000000
#define ADR_MTTCAN_TXBCIE 0x0E4
#define DEF_MTTCAN_TXBCIE 0x00000000
#define ADR_MTTCAN_TXEFC 0x0F0
#define DEF_MTTCAN_TXEFC 0x00000000
#define ADR_MTTCAN_TXEFS 0x0F4
#define DEF_MTTCAN_TXEFS 0x00000000
#define ADR_MTTCAN_TXEFA 0x0F8
#define DEF_MTTCAN_TXEFA 0x00000000
#define ADR_MTTCAN_TTTMC 0x100
#define DEF_MTTCAN_TTTMC 0x00000000
#define ADR_MTTCAN_TTRMC 0x104
#define DEF_MTTCAN_TTRMC 0x00000000
#define MTTCAN_TTRMC_MSK 0xDFFFFFFF
#define ADR_MTTCAN_TTOCF 0x108
#define DEF_MTTCAN_TTOCF 0x00010000
#define ADR_MTTCAN_TTMLM 0x10C
#define DEF_MTTCAN_TTMLM 0x00000000
#define ADR_MTTCAN_TURCF 0x110
#define DEF_MTTCAN_TURCF 0x10000000
#define ADR_MTTCAN_TTOCN 0x114
#define DEF_MTTCAN_TTOCN 0x00000000
#define ADR_MTTCAN_TTGTP 0x118
#define DEF_MTTCAN_TTGTP 0x00000000
#define ADR_MTTCAN_TTTMK 0x11C
#define DEF_MTTCAN_TTTMK 0x00000000
#define ADR_MTTCAN_TTIR 0x120
#define DEF_MTTCAN_TTIR 0x00000000
#define ADR_MTTCAN_TTIE 0x124
#define DEF_MTTCAN_TTIE 0x00000000
#define ADR_MTTCAN_TTILS 0x128
#define DEF_MTTCAN_TTILS 0x00000000
#define ADR_MTTCAN_TTOST 0x12C
#define DEF_MTTCAN_TTOST 0x00000080
#define ADR_MTTCAN_TURNA 0x130
#define DEF_MTTCAN_TURNA 0x00010000
#define ADR_MTTCAN_TTLGT 0x134
#define DEF_MTTCAN_TTLGT 0x00000000
#define ADR_MTTCAN_TTCTC 0x138
#define DEF_MTTCAN_TTCTC 0x003F0000
#define ADR_MTTCAN_TTCPT 0x13C
#define DEF_MTTCAN_TTCPT 0x00000000
#define ADR_MTTCAN_TTCSM 0x140
#define DEF_MTTCAN_TTCSM 0x00000000
#define MTT_CREL_DAY_SHIFT 0
#define MTT_CREL_DAY_MASK (((1<<8)-1) << MTT_CREL_DAY_SHIFT)
#define MTT_CREL_MON_SHIFT 8
#define MTT_CREL_MON_MASK (((1<<8)-1) << MTT_CREL_MON_SHIFT)
#define MTT_CREL_YEAR_SHIFT 16
#define MTT_CREL_YEAR_MASK (((1<<4)-1) << MTT_CREL_YEAR_SHIFT)
#define MTT_CREL_SUBS_SHIFT 20
#define MTT_CREL_SUBS_MASK (((1<<4)-1) << MTT_CREL_SUBS_SHIFT)
#define MTT_CREL_STEP_SHIFT 24
#define MTT_CREL_STEP_MASK (((1<<4)-1) << MTT_CREL_STEP_SHIFT)
#define MTT_CREL_REL_SHIFT 28
#define MTT_CREL_REL_MASK (((1<<4)-1) << MTT_CREL_REL_SHIFT)
#define MTT_DBTP_DSJW_SHIFT 0
#define MTT_DBTP_DSJW_MASK (((1<<4)-1) << MTT_DBTP_DSJW_SHIFT)
#define MTT_DBTP_DTSEG2_SHIFT 4
#define MTT_DBTP_DTSEG2_MASK (((1<<4)-1) << MTT_DBTP_DTSEG2_SHIFT)
#define MTT_DBTP_DTSEG1_SHIFT 8
#define MTT_DBTP_DTSEG1_MASK (((1<<5)-1) << MTT_DBTP_DTSEG1_SHIFT)
#define MTT_DBTP_DBRP_SHIFT 16
#define MTT_DBTP_DBRP_MASK (((1<<5)-1) << MTT_DBTP_DBRP_SHIFT)
#define MTT_DBTP_TDC_SHIFT 23
#define MTT_DBTP_TDC_MASK (((1<<1)-1) << MTT_DBTP_TDC_SHIFT)
#define MTT_TEST_TAM_SHIFT 0
#define MTT_TEST_TAM_MASK (((1<<1)-1) << MTT_TEST_TAM_SHIFT)
#define MTT_TEST_TAT_SHIFT 1
#define MTT_TEST_TAT_MASK (((1<<1)-1) << MTT_TEST_TAT_SHIFT)
#define MTT_TEST_CAM_SHIFT 2
#define MTT_TEST_CAM_MASK (((1<<1)-1) << MTT_TEST_CAM_SHIFT)
#define MTT_TEST_CAT_SHIFT 3
#define MTT_TEST_CAT_MASK (((1<<1)-1) << MTT_TEST_CAT_SHIFT)
#define MTT_TEST_LBCK_SHIFT 4
#define MTT_TEST_LBCK_MASK (((1<<1)-1) << MTT_TEST_LBCK_SHIFT)
#define MTT_TEST_TX_SHIFT 5
#define MTT_TEST_TX_MASK (((1<<2)-1) << MTT_TEST_TX_SHIFT)
#define MTT_TEST_RX_SHIFT 7
#define MTT_TEST_RX_MASK (((1<<1)-1) << MTT_TEST_RX_SHIFT)
#define MTT_CCCR_INIT_SHIFT 0
#define MTT_CCCR_INIT_MASK (((1<<1)-1) << MTT_CCCR_INIT_SHIFT)
#define MTT_CCCR_CCE_SHIFT 1
#define MTT_CCCR_CCE_MASK (((1<<1)-1) << MTT_CCCR_CCE_SHIFT)
#define MTT_CCCR_ASM_SHIFT 2
#define MTT_CCCR_ASM_MASK (((1<<1)-1) << MTT_CCCR_ASM_SHIFT)
#define MTT_CCCR_CSA_SHIFT 3
#define MTT_CCCR_CSA_MASK (((1<<1)-1) << MTT_CCCR_CSA_SHIFT)
#define MTT_CCCR_CSR_SHIFT 4
#define MTT_CCCR_CSR_MASK (((1<<1)-1) << MTT_CCCR_CSR_SHIFT)
#define MTT_CCCR_MON_SHIFT 5
#define MTT_CCCR_MON_MASK (((1<<1)-1) << MTT_CCCR_MON_SHIFT)
#define MTT_CCCR_DAR_SHIFT 6
#define MTT_CCCR_DAR_MASK (((1<<1)-1) << MTT_CCCR_DAR_SHIFT)
#define MTT_CCCR_TEST_SHIFT 7
#define MTT_CCCR_TEST_MASK (((1<<1)-1) << MTT_CCCR_TEST_SHIFT)
#define MTT_CCCR_FDOE_SHIFT 8
#define MTT_CCCR_FDOE_MASK (((1<<1)-1) << MTT_CCCR_FDOE_SHIFT)
#define MTT_CCCR_BRSE_SHIFT 9
#define MTT_CCCR_BRSE_MASK (((1<<1)-1) << MTT_CCCR_BRSE_SHIFT)
#define MTT_CCCR_PXHD_SHIFT 12
#define MTT_CCCR_PXHD_MASK (((1<<1)-1) << MTT_CCCR_PXHD_SHIFT)
#define MTT_CCCR_EFB1_SHIFT 13
#define MTT_CCCR_EFB1_MASK (((1<<1)-1) << MTT_CCCR_EFB1_SHIFT)
#define MTT_CCCR_TXP_SHIFT 14
#define MTT_CCCR_TXP_MASK (((1<<1)-1) << MTT_CCCR_TXP_SHIFT)
#define MTT_CCCR_NISO_SHIFT 15
#define MTT_CCCR_NISO_MASK (((1<<1)-1) << MTT_CCCR_NISO_SHIFT)
#define MTT_NBTP_NTSEG2_SHIFT 0
#define MTT_NBTP_NTSEG2_MASK (((1<<7)-1) << MTT_NBTP_NTSEG2_SHIFT)
#define MTT_NBTP_NTSEG1_SHIFT 8
#define MTT_NBTP_NTSEG1_MASK (((1<<8)-1) << MTT_NBTP_NTSEG1_SHIFT)
#define MTT_NBTP_NBRP_SHIFT 16
#define MTT_NBTP_NBRP_MASK (((1<<9)-1) << MTT_NBTP_NBRP_SHIFT)
#define MTT_NBTP_NSJW_SHIFT 25
#define MTT_NBTP_NSJW_MASK (((1<<7)-1) << MTT_NBTP_NSJW_SHIFT)
#define MTT_TSCC_TSS_SHIFT 0
#define MTT_TSCC_TSS_MASK (((1<<2)-1) << MTT_TSCC_TSS_SHIFT)
#define MTT_TSCC_TCP_SHIFT 16
#define MTT_TSCC_TCP_MASK (((1<<4)-1) << MTT_TSCC_TCP_SHIFT)
#define MTT_ECR_TEC_SHIFT 0
#define MTT_ECR_TEC_MASK (((1<<8)-1) << MTT_ECR_TEC_SHIFT)
#define MTT_ECR_REC_SHIFT 8
#define MTT_ECR_REC_MASK (((1<<7)-1) << MTT_ECR_REC_SHIFT)
#define MTT_ECR_RP_SHIFT 15
#define MTT_ECR_RP_MASK (((1<<1)-1) << MTT_ECR_RP_SHIFT)
#define MTT_ECR_CEL_SHIFT 16
#define MTT_ECR_CEL_MASK (((1<<8)-1) << MTT_ECR_CEL_SHIFT)
#define MTT_PSR_LEC_SHIFT 0
#define MTT_PSR_LEC_MASK (((1<<3)-1) << MTT_PSR_LEC_SHIFT)
#define MTT_PSR_ACT_SHIFT 3
#define MTT_PSR_ACT_MASK (((1<<2)-1) << MTT_PSR_ACT_SHIFT)
#define MTT_PSR_EP_SHIFT 5
#define MTT_PSR_EP_MASK (((1<<1)-1) << MTT_PSR_EP_SHIFT)
#define MTT_PSR_EW_SHIFT 6
#define MTT_PSR_EW_MASK (((1<<1)-1) << MTT_PSR_EW_SHIFT)
#define MTT_PSR_BO_SHIFT 7
#define MTT_PSR_BO_MASK (((1<<1)-1) << MTT_PSR_BO_SHIFT)
#define MTT_PSR_DLEC_SHIFT 8
#define MTT_PSR_DLEC_MASK (((1<<3)-1) << MTT_PSR_DLEC_SHIFT)
#define MTT_PSR_RESI_SHIFT 11
#define MTT_PSR_RESI_MASK (((1<<1)-1) << MTT_PSR_RESI_SHIFT)
#define MTT_PSR_RBRS_SHIFT 12
#define MTT_PSR_RBRS_MASK (((1<<1)-1) << MTT_PSR_RBRS_SHIFT)
#define MTT_PSR_RFDF_SHIFT 13
#define MTT_PSR_RFDF_MASK (((1<<1)-1) << MTT_PSR_RFDF_SHIFT)
#define MTT_PSR_PXE_SHIFT 14
#define MTT_PSR_PXE_MASK (((1<<1)-1) << MTT_PSR_PXE_SHIFT)
#define MTT_PSR_TDCV_SHIFT 16
#define MTT_PSR_TDCV_MASK (((1<<7)-1) << MTT_PSR_TDCV_SHIFT)
#define MTT_TDCR_TDCF_SHIFT 0
#define MTT_TDCR_TDCF_MASK (((1<<7)-1) << MTT_TDCR_TDCF_SHIFT)
#define MTT_TDCR_TDCO_SHIFT 8
#define MTT_TDCR_TDCO_MASK (((1<<7)-1) << MTT_TDCR_TDCO_SHIFT)
#define MTT_IR_RF0N_SHIFT 0
#define MTT_IR_RF0N_MASK (((1<<1)-1) << MTT_IR_RF0N_SHIFT)
#define MTT_IR_RF0W_SHIFT 1
#define MTT_IR_RF0W_MASK (((1<<1)-1) << MTT_IR_RF0W_SHIFT)
#define MTT_IR_RF0F_SHIFT 2
#define MTT_IR_RF0F_MASK (((1<<1)-1) << MTT_IR_RF0F_SHIFT)
#define MTT_IR_RF0L_SHIFT 3
#define MTT_IR_RF0L_MASK (((1<<1)-1) << MTT_IR_RF0L_SHIFT)
#define MTT_IR_RF1N_SHIFT 4
#define MTT_IR_RF1N_MASK (((1<<1)-1) << MTT_IR_RF1N_SHIFT)
#define MTT_IR_RF1W_SHIFT 5
#define MTT_IR_RF1W_MASK (((1<<1)-1) << MTT_IR_RF1W_SHIFT)
#define MTT_IR_RF1F_SHIFT 6
#define MTT_IR_RF1F_MASK (((1<<1)-1) << MTT_IR_RF1F_SHIFT)
#define MTT_IR_RF1L_SHIFT 7
#define MTT_IR_RF1L_MASK (((1<<1)-1) << MTT_IR_RF1L_SHIFT)
#define MTT_IR_HPM_SHIFT 8
#define MTT_IR_HPM_MASK (((1<<1)-1) << MTT_IR_HPM_SHIFT)
#define MTT_IR_TC_SHIFT 9
#define MTT_IR_TC_MASK (((1<<1)-1) << MTT_IR_TC_SHIFT)
#define MTT_IR_TCF_SHIFT 10
#define MTT_IR_TCF_MASK (((1<<1)-1) << MTT_IR_TCF_SHIFT)
#define MTT_IR_TFE_SHIFT 11
#define MTT_IR_TFE_MASK (((1<<1)-1) << MTT_IR_TFE_SHIFT)
#define MTT_IR_TEFN_SHIFT 12
#define MTT_IR_TEFN_MASK (((1<<1)-1) << MTT_IR_TEFN_SHIFT)
#define MTT_IR_TEFW_SHIFT 13
#define MTT_IR_TEFW_MASK (((1<<1)-1) << MTT_IR_TEFW_SHIFT)
#define MTT_IR_TEFF_SHIFT 14
#define MTT_IR_TEFF_MASK (((1<<1)-1) << MTT_IR_TEFF_SHIFT)
#define MTT_IR_TEFL_SHIFT 15
#define MTT_IR_TEFL_MASK (((1<<1)-1) << MTT_IR_TEFL_SHIFT)
#define MTT_IR_TSW_SHIFT 16
#define MTT_IR_TSW_MASK (((1<<1)-1) << MTT_IR_TSW_SHIFT)
#define MTT_IR_MRAF_SHIFT 17
#define MTT_IR_MRAF_MASK (((1<<1)-1) << MTT_IR_MRAF_SHIFT)
#define MTT_IR_TOO_SHIFT 18
#define MTT_IR_TOO_MASK (((1<<1)-1) << MTT_IR_TOO_SHIFT)
#define MTT_IR_DRX_SHIFT 19
#define MTT_IR_DRX_MASK (((1<<1)-1) << MTT_IR_DRX_SHIFT)
#define MTT_IR_BEC_SHIFT 20
#define MTT_IR_BEC_MASK (((1<<1)-1) << MTT_IR_BEC_SHIFT)
#define MTT_IR_BEU_SHIFT 21
#define MTT_IR_BEU_MASK (((1<<1)-1) << MTT_IR_BEU_SHIFT)
#define MTT_IR_ELO_SHIFT 22
#define MTT_IR_ELO_MASK (((1<<1)-1) << MTT_IR_ELO_SHIFT)
#define MTT_IR_EP_SHIFT 23
#define MTT_IR_EP_MASK (((1<<1)-1) << MTT_IR_EP_SHIFT)
#define MTT_IR_EW_SHIFT 24
#define MTT_IR_EW_MASK (((1<<1)-1) << MTT_IR_EW_SHIFT)
#define MTT_IR_BO_SHIFT 25
#define MTT_IR_BO_MASK (((1<<1)-1) << MTT_IR_BO_SHIFT)
#define MTT_IR_WDI_SHIFT 26
#define MTT_IR_WDI_MASK (((1<<1)-1) << MTT_IR_WDI_SHIFT)
#define MTT_IR_PEA_SHIFT 27
#define MTT_IR_PEA_MASK (((1<<1)-1) << MTT_IR_PEA_SHIFT)
#define MTT_IR_PED_SHIFT 28
#define MTT_IR_PED_MASK (((1<<1)-1) << MTT_IR_PED_SHIFT)
#define MTT_IR_ARA_SHIFT 29
#define MTT_IR_ARA_MASK (((1<<1)-1) << MTT_IR_ARA_SHIFT)
#define MTT_IE_RF0NE_SHIFT 0
#define MTT_IE_RF0NE_MASK (((1<<1)-1) << MTT_IE_RF0NE_SHIFT)
#define MTT_IE_RF0WE_SHIFT 1
#define MTT_IE_RF0WE_MASK (((1<<1)-1) << MTT_IE_RF0WE_SHIFT)
#define MTT_IE_RF0FE_SHIFT 2
#define MTT_IE_RF0FE_MASK (((1<<1)-1) << MTT_IE_RF0FE_SHIFT)
#define MTT_IE_RF0LE_SHIFT 3
#define MTT_IE_RF0LE_MASK (((1<<1)-1) << MTT_IE_RF0LE_SHIFT)
#define MTT_IE_RF1NE_SHIFT 4
#define MTT_IE_RF1NE_MASK (((1<<1)-1) << MTT_IE_RF1NE_SHIFT)
#define MTT_IE_RF1WE_SHIFT 5
#define MTT_IE_RF1WE_MASK (((1<<1)-1) << MTT_IE_RF1WE_SHIFT)
#define MTT_IE_RF1FE_SHIFT 6
#define MTT_IE_RF1FE_MASK (((1<<1)-1) << MTT_IE_RF1FE_SHIFT)
#define MTT_IE_RF1LE_SHIFT 7
#define MTT_IE_RF1LE_MASK (((1<<1)-1) << MTT_IE_RF1LE_SHIFT)
#define MTT_IE_HPME_SHIFT 8
#define MTT_IE_HPME_MASK (((1<<1)-1) << MTT_IE_HPME_SHIFT)
#define MTT_IE_TCE_SHIFT 9
#define MTT_IE_TCE_MASK (((1<<1)-1) << MTT_IE_TCE_SHIFT)
#define MTT_IE_TCFE_SHIFT 10
#define MTT_IE_TCFE_MASK (((1<<1)-1) << MTT_IE_TCFE_SHIFT)
#define MTT_IE_TFEE_SHIFT 11
#define MTT_IE_TFEE_MASK (((1<<1)-1) << MTT_IE_TFEE_SHIFT)
#define MTT_IE_TEFNE_SHIFT 12
#define MTT_IE_TEFNE_MASK (((1<<1)-1) << MTT_IE_TEFNE_SHIFT)
#define MTT_IE_TEFWE_SHIFT 13
#define MTT_IE_TEFWE_MASK (((1<<1)-1) << MTT_IE_TEFWE_SHIFT)
#define MTT_IE_TEFFE_SHIFT 14
#define MTT_IE_TEFFE_MASK (((1<<1)-1) << MTT_IE_TEFFE_SHIFT)
#define MTT_IE_TEFLE_SHIFT 15
#define MTT_IE_TEFLE_MASK (((1<<1)-1) << MTT_IE_TEFLE_SHIFT)
#define MTT_IE_TESWE_SHIFT 16
#define MTT_IE_TESWE_MASK (((1<<1)-1) << MTT_IE_TESWE_SHIFT)
#define MTT_IE_MRAFE_SHIFT 17
#define MTT_IE_MRAFE_MASK (((1<<1)-1) << MTT_IE_MRAFE_SHIFT)
#define MTT_IE_TOOE_SHIFT 18
#define MTT_IE_TOOE_MASK (((1<<1)-1) << MTT_IE_TOOE_SHIFT)
#define MTT_IE_DRXE_SHIFT 19
#define MTT_IE_DRXE_MASK (((1<<1)-1) << MTT_IE_DRXE_SHIFT)
#define MTT_IE_BECE_SHIFT 20
#define MTT_IE_BECE_MASK (((1<<1)-1) << MTT_IE_BECE_SHIFT)
#define MTT_IE_BEUE_SHIFT 21
#define MTT_IE_BEUE_MASK (((1<<1)-1) << MTT_IE_BEUE_SHIFT)
#define MTT_IE_ELOE_SHIFT 22
#define MTT_IE_ELOE_MASK (((1<<1)-1) << MTT_IE_ELOE_SHIFT)
#define MTT_IE_EPE_SHIFT 23
#define MTT_IE_EPE_MASK (((1<<1)-1) << MTT_IE_EPE_SHIFT)
#define MTT_IE_EWE_SHIFT 24
#define MTT_IE_EWE_MASK (((1<<1)-1) << MTT_IE_EWE_SHIFT)
#define MTT_IE_BOE_SHIFT 25
#define MTT_IE_BOE_MASK (((1<<1)-1) << MTT_IE_BOE_SHIFT)
#define MTT_IE_WDIE_SHIFT 26
#define MTT_IE_WDIE_MASK (((1<<1)-1) << MTT_IE_WDIE_SHIFT)
#define MTT_IE_PEAE_SHIFT 27
#define MTT_IE_PEAE_MASK (((1<<1)-1) << MTT_IE_PEAE_SHIFT)
#define MTT_IE_PEDE_SHIFT 28
#define MTT_IE_PEDE_MASK (((1<<1)-1) << MTT_IE_PEDE_SHIFT)
#define MTT_IE_ARAE_SHIFT 29
#define MTT_IE_ARAE_MASK (((1<<1)-1) << MTT_IE_ARAE_SHIFT)
#define MTT_GFC_RRFE_SHIFT 0
#define MTT_GFC_RRFE_MASK (((1<<1)-1) << MTT_GFC_RRFE_SHIFT)
#define MTT_GFC_RRFS_SHIFT 1
#define MTT_GFC_RRFS_MASK (((1<<1)-1) << MTT_GFC_RRFS_SHIFT)
#define MTT_GFC_ANFE_SHIFT 2
#define MTT_GFC_ANFE_MASK (((1<<2)-1) << MTT_GFC_ANFE_SHIFT)
#define MTT_GFC_ANFS_SHIFT 4
#define MTT_GFC_ANFS_MASK (((1<<2)-1) << MTT_GFC_ANFS_SHIFT)
#define MTT_SIDFC_FLSSA_SHIFT 2
#define MTT_SIDFC_FLSSA_MASK (((1<<14)-1) << MTT_SIDFC_FLSSA_SHIFT)
#define MTT_SIDFC_LSS_SHIFT 16
#define MTT_SIDFC_LSS_MASK (((1<<8)-1) << MTT_SIDFC_LSS_SHIFT)
#define MTT_XIDFC_FLESA_SHIFT 2
#define MTT_XIDFC_FLESA_MASK (((1<<14)-1) << MTT_XIDFC_FLESA_SHIFT)
#define MTT_XIDFC_LSE_SHIFT 16
#define MTT_XIDFC_LSE_MASK (((1<<7)-1) << MTT_XIDFC_LSE_SHIFT)
#define MTT_XIDAM_EIDM_SHIFT 0
#define MTT_XIDAM_EIDM_MASK (((1<<29)-1) << MTT_XIDAM_EIDM_SHIFT)
#define MTT_HPMS_BIDX_SHIFT 0
#define MTT_HPMS_BIDX_MASK (((1<<6)-1) << MTT_HPMS_BIDX_SHIFT)
#define MTT_HPMS_MSI_SHIFT 6
#define MTT_HPMS_MSI_MASK (((1<<2)-1) << MTT_HPMS_MSI_SHIFT)
#define MTT_HPMS_FIDX_SHIFT 8
#define MTT_HPMS_FIDX_MASK (((1<<7)-1) << MTT_HPMS_FIDX_SHIFT)
#define MTT_HPMS_FLST_SHIFT 15
#define MTT_HPMS_FLST_MASK (((1<<1)-1) << MTT_HPMS_FLST_SHIFT)
#define MTT_RXF0C_F0SA_SHIFT 2
#define MTT_RXF0C_F0SA_MASK (((1<<14)-1) << MTT_RXF0C_F0SA_SHIFT)
#define MTT_RXF0C_F0S_SHIFT 16
#define MTT_RXF0C_F0S_MASK (((1<<7)-1) << MTT_RXF0C_F0S_SHIFT)
#define MTT_RXF0C_F0WM_SHIFT 24
#define MTT_RXF0C_F0WM_MASK (((1<<7)-1) << MTT_RXF0C_F0WM_SHIFT)
#define MTT_RXF0C_F0OM_SHIFT 31
#define MTT_RXF0C_F0OM_MASK (((1<<1)-1) << MTT_RXF0C_F0OM_SHIFT)
#define MTT_RXF0S_F0FL_SHIFT 0
#define MTT_RXF0S_F0FL_MASK (((1<<7)-1) << MTT_RXF0S_F0FL_SHIFT)
#define MTT_RXF0S_F0GI_SHIFT 8
#define MTT_RXF0S_F0GI_MASK (((1<<6)-1) << MTT_RXF0S_F0GI_SHIFT)
#define MTT_RXF0S_F0PI_SHIFT 16
#define MTT_RXF0S_F0PI_MASK (((1<<6)-1) << MTT_RXF0S_F0PI_SHIFT)
#define MTT_RXF0S_F0F_SHIFT 24
#define MTT_RXF0S_F0F_MASK (((1<<1)-1) << MTT_RXF0S_F0F_SHIFT)
#define MTT_RXF0S_RF0L_SHIFT 25
#define MTT_RXF0S_RF0L_MASK (((1<<1)-1) << MTT_RXF0S_RF0L_SHIFT)
#define MTT_RXF0A_F0AI_SHIFT 0
#define MTT_RXF0A_F0AI_MASK (((1<<6)-1) << MTT_RXF0A_F0AI_SHIFT)
#define MTT_RXBC_RBSA_SHIFT 2
#define MTT_RXBC_RBSA_MASK (((1<<14)-1) << MTT_RXBC_RBSA_SHIFT)
#define MTT_RXF1C_F1SA_SHIFT 2
#define MTT_RXF1C_F1SA_MASK (((1<<14)-1) << MTT_RXF1C_F1SA_SHIFT)
#define MTT_RXF1C_F1S_SHIFT 16
#define MTT_RXF1C_F1S_MASK (((1<<7)-1) << MTT_RXF1C_F1S_SHIFT)
#define MTT_RXF1C_F1WM_SHIFT 24
#define MTT_RXF1C_F1WM_MASK (((1<<7)-1) << MTT_RXF1C_F1WM_SHIFT)
#define MTT_RXF1C_F1OM_SHIFT 31
#define MTT_RXF1C_F1OM_MASK (((1<<1)-1) << MTT_RXF1C_F1OM_SHIFT)
#define MTT_RXF1S_F1FL_SHIFT 0
#define MTT_RXF1S_F1FL_MASK (((1<<7)-1) << MTT_RXF1S_F1FL_SHIFT)
#define MTT_RXF1S_F1GI_SHIFT 8
#define MTT_RXF1S_F1GI_MASK (((1<<6)-1) << MTT_RXF1S_F1GI_SHIFT)
#define MTT_RXF1S_F1PI_SHIFT 16
#define MTT_RXF1S_F1PI_MASK (((1<<6)-1) << MTT_RXF1S_F1PI_SHIFT)
#define MTT_RXF1S_F1F_SHIFT 24
#define MTT_RXF1S_F1F_MASK (((1<<1)-1) << MTT_RXF1S_F1F_SHIFT)
#define MTT_RXF1S_RF1L_SHIFT 25
#define MTT_RXF1S_RF1L_MASK (((1<<1)-1) << MTT_RXF1S_RF1L_SHIFT)
#define MTT_RXF1S_DMS_SHIFT 30
#define MTT_RXF1S_DMS_MASK (((1<<2)-1) << MTT_RXF1S_DMS_SHIFT)
#define MTT_RXF1A_F1AI_SHIFT 0
#define MTT_RXF1A_F1AI_MASK (((1<<6)-1) << MTT_RXF1A_F1AI_SHIFT)
#define MTT_RXESC_F0DS_SHIFT 0
#define MTT_RXESC_F0DS_MASK (((1<<3)-1) << MTT_RXESC_F0DS_SHIFT)
#define MTT_RXESC_F1DS_SHIFT 4
#define MTT_RXESC_F1DS_MASK (((1<<3)-1) << MTT_RXESC_F1DS_SHIFT)
#define MTT_RXESC_RBDS_SHIFT 8
#define MTT_RXESC_RBDS_MASK (((1<<3)-1) << MTT_RXESC_RBDS_SHIFT)
#define MTT_TXESC_TBDS_SHIFT 0
#define MTT_TXESC_TBDS_MASK (((1<<3)-1) << MTT_TXESC_TBDS_SHIFT)
#define MTT_TXBC_TBSA_SHIFT 2
#define MTT_TXBC_TBSA_MASK (((1<<14)-1) << MTT_TXBC_TBSA_SHIFT)
#define MTT_TXBC_NDTB_SHIFT 16
#define MTT_TXBC_NDTB_MASK (((1<<6)-1) << MTT_TXBC_NDTB_SHIFT)
#define MTT_TXBC_TFQS_SHIFT 24
#define MTT_TXBC_TFQS_MASK (((1<<6)-1) << MTT_TXBC_TFQS_SHIFT)
#define MTT_TXBC_TFQM_SHIFT 30
#define MTT_TXBC_TFQM_MASK (((1<<1)-1) << MTT_TXBC_TFQM_SHIFT)
#define MTT_TXFQS_TFFL_SHIFT 0
#define MTT_TXFQS_TFFL_MASK (((1<<6)-1) << MTT_TXFQS_TFFL_SHIFT)
#define MTT_TXFQS_TFGI_SHIFT 8
#define MTT_TXFQS_TFGI_MASK (((1<<5)-1) << MTT_TXFQS_TFGI_SHIFT)
#define MTT_TXFQS_TFQPI_SHIFT 16
#define MTT_TXFQS_TFQPI_MASK (((1<<5)-1) << MTT_TXFQS_TFQPI_SHIFT)
#define MTT_TXFQS_TFQF_SHIFT 21
#define MTT_TXFQS_TFQF_MASK (((1<<1)-1) << MTT_TXFQS_TFQF_SHIFT)
#define MTT_TXEFC_EFSA_SHIFT 2
#define MTT_TXEFC_EFSA_MASK (((1<<14)-1) << MTT_TXEFC_EFSA_SHIFT)
#define MTT_TXEFC_EFS_SHIFT 16
#define MTT_TXEFC_EFS_MASK (((1<<6)-1) << MTT_TXEFC_EFS_SHIFT)
#define MTT_TXEFC_EFWM_SHIFT 24
#define MTT_TXEFC_EFWM_MASK (((1<<6)-1) << MTT_TXEFC_EFWM_SHIFT)
#define MTT_TXEFS_EFFL_SHIFT 0
#define MTT_TXEFS_EFFL_MASK (((1<<6)-1) << MTT_TXEFS_EFFL_SHIFT)
#define MTT_TXEFS_EFGI_SHIFT 8
#define MTT_TXEFS_EFGI_MASK (((1<<5)-1) << MTT_TXEFS_EFGI_SHIFT)
#define MTT_TXEFS_EFPI_SHIFT 16
#define MTT_TXEFS_EFPI_MASK (((1<<5)-1) << MTT_TXEFS_EFPI_SHIFT)
#define MTT_TXEFS_EFF_SHIFT 24
#define MTT_TXEFS_EFF_MASK (((1<<1)-1) << MTT_TXEFS_EFF_SHIFT)
#define MTT_TXEFS_TFFL_SHIFT 25
#define MTT_TXEFS_TFFL_MASK (((1<<1)-1) << MTT_TXEFS_TFFL_SHIFT)
#define MTT_TXEFA_EFAI_SHIFT 0
#define MTT_TXEFA_EFAI_MASK (((1<<5)-1) << MTT_TXEFA_EFAI_SHIFT)
#define MTT_TTTMC_TMSA_SHIFT 2
#define MTT_TTTMC_TMSA_MASK (((1<<14)-1) << MTT_TTTMC_TMSA_SHIFT)
#define MTT_TTTMC_TME_SHIFT 16
#define MTT_TTTMC_TME_MASK (((1<<7)-1) << MTT_TTTMC_TME_SHIFT)
#define MTT_TTRMC_RID_SHIFT 0
#define MTT_TTRMC_RID_MASK (((1<<29)-1) << MTT_TTRMC_RID_SHIFT)
#define MTT_TTRMC_XTD_SHIFT 30
#define MTT_TTRMC_XTD_MASK (((1<<1)-1) << MTT_TTRMC_XTD_SHIFT)
#define MTT_TTRMC_RMPS_SHIFT 31
#define MTT_TTRMC_RMPS_MASK (((1<<1)-1) << MTT_TTRMC_RMPS_SHIFT)
#define MTT_TTOCF_OM_SHIFT 0
#define MTT_TTOCF_OM_MASK (((1<<2)-1) << MTT_TTOCF_OM_SHIFT)
#define MTT_TTOCF_GEN_SHIFT 3
#define MTT_TTOCF_GEN_MASK (((1<<1)-1) << MTT_TTOCF_GEN_SHIFT)
#define MTT_TTOCF_TM_SHIFT 4
#define MTT_TTOCF_TM_MASK (((1<<1)-1) << MTT_TTOCF_TM_SHIFT)
#define MTT_TTOCF_LDSDL_SHIFT 5
#define MTT_TTOCF_LDSDL_MASK (((1<<3)-1) << MTT_TTOCF_LDSDL_SHIFT)
#define MTT_TTOCF_IRTO_SHIFT 8
#define MTT_TTOCF_IRTO_MASK (((1<<7)-1) << MTT_TTOCF_IRTO_SHIFT)
#define MTT_TTOCF_EECS_SHIFT 15
#define MTT_TTOCF_EECS_MASK (((1<<1)-1) << MTT_TTOCF_EECS_SHIFT)
#define MTT_TTOCF_AWL_SHIFT 16
#define MTT_TTOCF_AWL_MASK (((1<<8)-1) << MTT_TTOCF_AWL_SHIFT)
#define MTT_TTOCF_EGTF_SHIFT 24
#define MTT_TTOCF_EGTF_MASK (((1<<1)-1) << MTT_TTOCF_EGTF_SHIFT)
#define MTT_TTOCF_ECC_SHIFT 25
#define MTT_TTOCF_ECC_MASK (((1<<1)-1) << MTT_TTOCF_ECC_SHIFT)
#define MTT_TTOCF_EVTP_SHIFT 26
#define MTT_TTOCF_EVTP_MASK (((1<<1)-1) << MTT_TTOCF_EVTP_SHIFT)
#define MTT_TTMLM_CCM_SHIFT 0
#define MTT_TTMLM_CCM_MASK (((1<<6)-1) << MTT_TTMLM_CCM_SHIFT)
#define MTT_TTMLM_CSS_SHIFT 6
#define MTT_TTMLM_CSS_MASK (((1<<2)-1) << MTT_TTMLM_CSS_SHIFT)
#define MTT_TTMLM_TXEW_SHIFT 8
#define MTT_TTMLM_TXEW_MASK (((1<<4)-1) << MTT_TTMLM_TXEW_SHIFT)
#define MTT_TTMLM_ENTT_SHIFT 16
#define MTT_TTMLM_ENTT_MASK (((1<<12)-1) << MTT_TTMLM_ENTT_SHIFT)
#define MTT_TURCF_NCL_SHIFT 0
#define MTT_TURCF_NCL_MASK (((1<<16)-1) << MTT_TURCF_NCL_SHIFT)
#define MTT_TURCF_DC_SHIFT 16
#define MTT_TURCF_DC_MASK (((1<<14)-1) << MTT_TURCF_DC_SHIFT)
#define MTT_TURCF_ELT_SHIFT 31
#define MTT_TURCF_ELT_MASK (((1<<1)-1) << MTT_TURCF_ELT_SHIFT)
#define MTT_TTOCN_SGT_SHIFT 0
#define MTT_TTOCN_SGT_MASK (((1<<1)-1) << MTT_TTOCN_SGT_SHIFT)
#define MTT_TTOCN_ECS_SHIFT 1
#define MTT_TTOCN_ECS_MASK (((1<<1)-1) << MTT_TTOCN_ECS_SHIFT)
#define MTT_TTOCN_SWP_SHIFT 2
#define MTT_TTOCN_SWP_MASK (((1<<1)-1) << MTT_TTOCN_SWP_SHIFT)
#define MTT_TTOCN_SWS_SHIFT 3
#define MTT_TTOCN_SWS_MASK (((1<<2)-1) << MTT_TTOCN_SWS_SHIFT)
#define MTT_TTOCN_RTIE_SHIFT 5
#define MTT_TTOCN_RTIE_MASK (((1<<1)-1) << MTT_TTOCN_RTIE_SHIFT)
#define MTT_TTOCN_TMC_SHIFT 6
#define MTT_TTOCN_TMC_MASK (((1<<2)-1) << MTT_TTOCN_TMC_SHIFT)
#define MTT_TTOCN_TTIE_SHIFT 8
#define MTT_TTOCN_TTIE_MASK (((1<<1)-1) << MTT_TTOCN_TTIE_SHIFT)
#define MTT_TTOCN_GCS_SHIFT 9
#define MTT_TTOCN_GCS_MASK (((1<<1)-1) << MTT_TTOCN_GCS_SHIFT)
#define MTT_TTOCN_FGP_SHIFT 10
#define MTT_TTOCN_FGP_MASK (((1<<1)-1) << MTT_TTOCN_FGP_SHIFT)
#define MTT_TTOCN_TMG_SHIFT 11
#define MTT_TTOCN_TMG_MASK (((1<<1)-1) << MTT_TTOCN_TMG_SHIFT)
#define MTT_TTOCN_NIG_SHIFT 12
#define MTT_TTOCN_NIG_MASK (((1<<1)-1) << MTT_TTOCN_NIG_SHIFT)
#define MTT_TTOCN_ESCN_SHIFT 13
#define MTT_TTOCN_ESCN_MASK (((1<<1)-1) << MTT_TTOCN_ESCN_SHIFT)
#define MTT_TTOCN_LCKC_SHIFT 15
#define MTT_TTOCN_LCKC_MASK (((1<<1)-1) << MTT_TTOCN_LCKC_SHIFT)
#define MTT_TTGTP_TP_SHIFT 0
#define MTT_TTGTP_TP_MASK (((1<<16)-1) << MTT_TTGTP_TP_SHIFT)
#define MTT_TTGTP_16_SHIFT 16
#define MTT_TTGTP_16_MASK (((1<<)-1) << MTT_TTGTP_16_SHIFT)
#define MTT_TTTMK_TM_SHIFT 0
#define MTT_TTTMK_TM_MASK (((1<<16)-1) << MTT_TTTMK_TM_SHIFT)
#define MTT_TTTMK_TICC_SHIFT 16
#define MTT_TTTMK_TICC_MASK (((1<<7)-1) << MTT_TTTMK_TICC_SHIFT)
#define MTT_TTTMK_LCKM_SHIFT 31
#define MTT_TTTMK_LCKM_MASK (((1<<1)-1) << MTT_TTTMK_LCKM_SHIFT)
#define MTT_TTIR_SBC_SHIFT 0
#define MTT_TTIR_SBC_MASK (((1<<1)-1) << MTT_TTIR_SBC_SHIFT)
#define MTT_TTIR_SMC_SHIFT 1
#define MTT_TTIR_SMC_MASK (((1<<1)-1) << MTT_TTIR_SMC_SHIFT)
#define MTT_TTIR_CSM_SHIFT 2
#define MTT_TTIR_CSM_MASK (((1<<1)-1) << MTT_TTIR_CSM_SHIFT)
#define MTT_TTIR_SOG_SHIFT 3
#define MTT_TTIR_SOG_MASK (((1<<1)-1) << MTT_TTIR_SOG_SHIFT)
#define MTT_TTIR_RTMI_SHIFT 4
#define MTT_TTIR_RTMI_MASK (((1<<1)-1) << MTT_TTIR_RTMI_SHIFT)
#define MTT_TTIR_TTMI_SHIFT 5
#define MTT_TTIR_TTMI_MASK (((1<<1)-1) << MTT_TTIR_TTMI_SHIFT)
#define MTT_TTIR_SWE_SHIFT 6
#define MTT_TTIR_SWE_MASK (((1<<1)-1) << MTT_TTIR_SWE_SHIFT)
#define MTT_TTIR_GTW_SHIFT 7
#define MTT_TTIR_GTW_MASK (((1<<1)-1) << MTT_TTIR_GTW_SHIFT)
#define MTT_TTIR_GTD_SHIFT 8
#define MTT_TTIR_GTD_MASK (((1<<1)-1) << MTT_TTIR_GTD_SHIFT)
#define MTT_TTIR_GTE_SHIFT 9
#define MTT_TTIR_GTE_MASK (((1<<1)-1) << MTT_TTIR_GTE_SHIFT)
#define MTT_TTIR_TXU_SHIFT 10
#define MTT_TTIR_TXU_MASK (((1<<1)-1) << MTT_TTIR_TXU_SHIFT)
#define MTT_TTIR_TXO_SHIFT 11
#define MTT_TTIR_TXO_MASK (((1<<1)-1) << MTT_TTIR_TXO_SHIFT)
#define MTT_TTIR_SE1_SHIFT 12
#define MTT_TTIR_SE1_MASK (((1<<1)-1) << MTT_TTIR_SE1_SHIFT)
#define MTT_TTIR_SE2_SHIFT 13
#define MTT_TTIR_SE2_MASK (((1<<1)-1) << MTT_TTIR_SE2_SHIFT)
#define MTT_TTIR_ELC_SHIFT 14
#define MTT_TTIR_ELC_MASK (((1<<1)-1) << MTT_TTIR_ELC_SHIFT)
#define MTT_TTIR_IWT_SHIFT 15
#define MTT_TTIR_IWT_MASK (((1<<1)-1) << MTT_TTIR_IWT_SHIFT)
#define MTT_TTIR_WT_SHIFT 16
#define MTT_TTIR_WT_MASK (((1<<1)-1) << MTT_TTIR_WT_SHIFT)
#define MTT_TTIR_AW_SHIFT 17
#define MTT_TTIR_AW_MASK (((1<<1)-1) << MTT_TTIR_AW_SHIFT)
#define MTT_TTIR_CER_SHIFT 18
#define MTT_TTIR_CER_MASK (((1<<1)-1) << MTT_TTIR_CER_SHIFT)
#define MTT_TTIRE_SBCE_SHIFT 0
#define MTT_TTIRE_SBCE_MASK (((1<<1)-1) << MTT_TTIRE_SBCE_SHIFT)
#define MTT_TTIRE_SMCE_SHIFT 1
#define MTT_TTIRE_SMCE_MASK (((1<<1)-1) << MTT_TTIRE_SMCE_SHIFT)
#define MTT_TTIRE_CSME_SHIFT 2
#define MTT_TTIRE_CSME_MASK (((1<<1)-1) << MTT_TTIRE_CSME_SHIFT)
#define MTT_TTIRE_SOGE_SHIFT 3
#define MTT_TTIRE_SOGE_MASK (((1<<1)-1) << MTT_TTIRE_SOGE_SHIFT)
#define MTT_TTIRE_RTMIE_SHIFT 4
#define MTT_TTIRE_RTMIE_MASK (((1<<1)-1) << MTT_TTIRE_RTMIE_SHIFT)
#define MTT_TTIRE_TTMIE_SHIFT 5
#define MTT_TTIRE_TTMIE_MASK (((1<<1)-1) << MTT_TTIRE_TTMIE_SHIFT)
#define MTT_TTIRE_SWEE_SHIFT 6
#define MTT_TTIRE_SWEE_MASK (((1<<1)-1) << MTT_TTIRE_SWEE_SHIFT)
#define MTT_TTIRE_GTWE_SHIFT 7
#define MTT_TTIRE_GTWE_MASK (((1<<1)-1) << MTT_TTIRE_GTWE_SHIFT)
#define MTT_TTIRE_GTDE_SHIFT 8
#define MTT_TTIRE_GTDE_MASK (((1<<1)-1) << MTT_TTIRE_GTDE_SHIFT)
#define MTT_TTIRE_GTEE_SHIFT 9
#define MTT_TTIRE_GTEE_MASK (((1<<1)-1) << MTT_TTIRE_GTEE_SHIFT)
#define MTT_TTIRE_TXUE_SHIFT 10
#define MTT_TTIRE_TXUE_MASK (((1<<1)-1) << MTT_TTIRE_TXUE_SHIFT)
#define MTT_TTIRE_TXOE_SHIFT 11
#define MTT_TTIRE_TXOE_MASK (((1<<1)-1) << MTT_TTIRE_TXOE_SHIFT)
#define MTT_TTIRE_SE1E_SHIFT 12
#define MTT_TTIRE_SE1E_MASK (((1<<1)-1) << MTT_TTIRE_SE1E_SHIFT)
#define MTT_TTIRE_SE2E_SHIFT 13
#define MTT_TTIRE_SE2E_MASK (((1<<1)-1) << MTT_TTIRE_SE2E_SHIFT)
#define MTT_TTIRE_ELCE_SHIFT 14
#define MTT_TTIRE_ELCE_MASK (((1<<1)-1) << MTT_TTIRE_ELCE_SHIFT)
#define MTT_TTIRE_IWTE_SHIFT 15
#define MTT_TTIRE_IWTE_MASK (((1<<1)-1) << MTT_TTIRE_IWTE_SHIFT)
#define MTT_TTIRE_WTE_SHIFT 16
#define MTT_TTIRE_WTE_MASK (((1<<1)-1) << MTT_TTIRE_WTE_SHIFT)
#define MTT_TTIRE_AWE_SHIFT 17
#define MTT_TTIRE_AWE_MASK (((1<<1)-1) << MTT_TTIRE_AWE_SHIFT)
#define MTT_TTIRE_CERE_SHIFT 18
#define MTT_TTIRE_CERE_MASK (((1<<1)-1) << MTT_TTIRE_CERE_SHIFT)
#define MTT_STD_FLTR_SFID2_SHIFT 0
#define MTT_STD_FLTR_SFID2_MASK (((1<<11)-1) << MTT_STD_FLTR_SFID2_SHIFT)
#define MTT_STD_FLTR_SFID1_SHIFT 16
#define MTT_STD_FLTR_SFID1_MASK (((1<<11)-1) << MTT_STD_FLTR_SFID1_SHIFT)
#define MTT_STD_FLTR_SFEC_SHIFT 27
#define MTT_STD_FLTR_SFEC_MASK (((1<<3)-1) << MTT_STD_FLTR_SFEC_SHIFT)
#define MTT_STD_FLTR_SFT_SHIFT 30
#define MTT_STD_FLTR_SFT_MASK (((1<<2)-1) << MTT_STD_FLTR_SFT_SHIFT)
#define MTT_XTD_FLTR_F1_EFID2_SHIFT 0
#define MTT_XTD_FLTR_F1_EFID2_MASK (((1<<29)-1) << MTT_XTD_FLTR_F1_EFID2_SHIFT)
#define MTT_XTD_FLTR_F1_EFT_SHIFT 30
#define MTT_XTD_FLTR_F1_EFT_MASK (((1<<2)-1) << MTT_XTD_FLTR_F1_EFT_SHIFT)
#define MTT_XTD_FLTR_F0_EFID1_SHIFT 0
#define MTT_XTD_FLTR_F0_EFID1_MASK (((1<<29)-1) << MTT_XTD_FLTR_F0_EFID1_SHIFT)
#define MTT_XTD_FLTR_F0_EFEC_SHIFT 29
#define MTT_XTD_FLTR_F0_EFEC_MASK (((1<<3)-1) << MTT_XTD_FLTR_F0_EFEC_SHIFT)
#define MTT_TXEVT_ELE_F1_TXTS_SHIFT 0
#define MTT_TXEVT_ELE_F1_TXTS_MASK (((1<<16)-1) << MTT_TXEVT_ELE_F1_TXTS_SHIFT)
#define MTT_TXEVT_ELE_F1_DLC_SHIFT 16
#define MTT_TXEVT_ELE_F1_DLC_MASK (((1<<4)-1) << MTT_TXEVT_ELE_F1_DLC_SHIFT)
#define MTT_TXEVT_ELE_F1_BRS_SHIFT 20
#define MTT_TXEVT_ELE_F1_BRS_MASK (((1<<1)-1) << MTT_TXEVT_ELE_F1_BRS_SHIFT)
#define MTT_TXEVT_ELE_F1_FDF_SHIFT 21
#define MTT_TXEVT_ELE_F1_FDF_MASK (((1<<1)-1) << MTT_TXEVT_ELE_F1_FDF_SHIFT)
#define MTT_TXEVT_ELE_F1_ET_SHIFT 22
#define MTT_TXEVT_ELE_F1_ET_MASK (((1<<2)-1) << MTT_TXEVT_ELE_F1_ET_SHIFT)
#define MTT_TXEVT_ELE_F1_MM_SHIFT 24
#define MTT_TXEVT_ELE_F1_MM_MASK (((1<<8)-1) << MTT_TXEVT_ELE_F1_MM_SHIFT)
#define MTT_TXEVT_ELE_F0_ID_SHIFT 0
#define MTT_TXEVT_ELE_F0_ID_MASK (((1<<29)-1) << MTT_TXEVT_ELE_F0_ID_SHIFT)
#define MTT_TXEVT_ELE_F0_RTR_SHIFT 29
#define MTT_TXEVT_ELE_F0_RTR_MASK (((1<<1)-1) << MTT_TXEVT_ELE_F0_RTR_SHIFT)
#define MTT_TXEVT_ELE_F0_XTD_SHIFT 30
#define MTT_TXEVT_ELE_F0_XTD_MASK (((1<<1)-1) << MTT_TXEVT_ELE_F0_XTD_SHIFT)
#define MTT_TXEVT_ELE_F0_ESI_SHIFT 31
#define MTT_TXEVT_ELE_F0_ESI_MASK (((1<<1)-1) << MTT_TXEVT_ELE_F0_ESI_SHIFT)
#define MTT_TRIG_ELE_F1_MSC_SHIFT 0
#define MTT_TRIG_ELE_F1_MSC_MASK (((1<<3)-1) << MTT_TRIG_ELE_F1_MSC_SHIFT)
#define MTT_TRIG_ELE_F1_MNR_SHIFT 16
#define MTT_TRIG_ELE_F1_MNR_MASK (((1<<7)-1) << MTT_TRIG_ELE_F1_MNR_SHIFT)
#define MTT_TRIG_ELE_F1_FTYPE_SHIFT 23
#define MTT_TRIG_ELE_F1_FTYPE_MASK (((1<<1)-1) << MTT_TRIG_ELE_F1_FTYPE_SHIFT)
#define MTT_TRIG_ELE_F0_TYPE_SHIFT 0
#define MTT_TRIG_ELE_F0_TYPE_MASK (((1<<4)-1) << MTT_TRIG_ELE_F0_TYPE_SHIFT)
#define MTT_TRIG_ELE_F0_TMEX_SHIFT 4
#define MTT_TRIG_ELE_F0_TMEX_MASK (((1<<1)-1) << MTT_TRIG_ELE_F0_TMEX_SHIFT)
#define MTT_TRIG_ELE_F0_TMIN_SHIFT 5
#define MTT_TRIG_ELE_F0_TMIN_MASK (((1<<1)-1) << MTT_TRIG_ELE_F0_TMIN_SHIFT)
#define MTT_TRIG_ELE_F0_ASC_SHIFT 6
#define MTT_TRIG_ELE_F0_ASC_MASK (((1<<2)-1) << MTT_TRIG_ELE_F0_ASC_SHIFT)
#define MTT_TRIG_ELE_F0_CC_SHIFT 8
#define MTT_TRIG_ELE_F0_CC_MASK (((1<<7)-1) << MTT_TRIG_ELE_F0_CC_SHIFT)
#define MTT_TRIG_ELE_F0_TM_SHIFT 16
#define MTT_TRIG_ELE_F0_TM_MASK (((1<<16)-1) << MTT_TRIG_ELE_F0_TM_SHIFT)
/* Extended Message ID Filter */
struct mttcan_xtd_id_filt_element {
unsigned int f1;
unsigned int f0;
};
/* Tx Event FIFO Element */
struct mttcan_tx_evt_element {
unsigned int f1;
unsigned int f0;
};
struct mttcan_trig_mem_element {
unsigned int f1;
unsigned int f0;
};
/* Rx Buffer */
#define RX_BUF_ESI BIT(31)
#define RX_BUF_XTD BIT(30)
#define RX_BUF_RTR BIT(29)
#define RX_BUF_STDID_SHIFT 18
#define RX_BUF_STDID_MASK (((1<<11)-1) << RX_BUF_STDID_SHIFT)
#define RX_BUF_EXTID_MASK ((1<<29)-1)
#define RX_BUF_ANMF BIT(31)
#define RX_BUF_FIDX_SHIFT 24
#define RX_BUF_FIDX_MASK (((1<<7)-1) << RX_BUF_FIDX_SHIFT)
#define RX_BUF_FDF BIT(21)
#define RX_BUF_BRS BIT(20)
#define RX_BUF_DLC_SHIFT 16
#define RX_BUF_DLC_MASK (((1<<4)-1) << RX_BUF_DLC_SHIFT)
#define RX_BUF_RXTS_SHIFT 0
#define RX_BUF_RXTS_MASK (((1<<16)-1) << RX_BUF_RXTS_SHIFT)
/* Tx Buffer */
#define TX_BUF_ESI BIT(31)
#define TX_BUF_XTD BIT(30)
#define TX_BUF_RTR BIT(29)
#define TX_BUF_STDID_SHIFT 18
#define TX_BUF_STDID_MASK (((1<<11)-1) << TX_BUF_STDID_SHIFT)
#define TX_BUF_EXTID_MASK ((1<<29)-1)
#define TX_BUF_MM_SHIFT 24
#define TX_BUF_MM_MASK (0xFF << TX_BUF_MM_SHIFT)
#define TX_BUF_EFC BIT(23)
#define TX_BUF_FDF BIT(21)
#define TX_BUF_BRS BIT(20)
#define TX_BUF_DLC_SHIFT 16
#define TX_BUF_DLC_MASK (0xF << TX_BUF_DLC_SHIFT)
/* Glue logic apperature */
#define ADDR_M_TTCAN_IR 0x00
#define ADDR_M_TTCAN_TTIR 0x04
#define ADDR_M_TTCAN_TXBRP 0x08
#define ADDR_M_TTCAN_FD_DATA 0x0C
#define ADDR_M_TTCAN_STATUS_REG 0x10
#define ADDR_M_TTCAN_CNTRL_REG 0x14
#define ADDR_M_TTCAN_DMA_INTF0 0x18
#define ADDR_M_TTCAN_CLK_STOP 0x1C
#define ADDR_M_TTCAN_HSM_MASK0 0x20
#define ADDR_M_TTCAN_HSM_MASK1 0x24
#define ADDR_M_TTCAN_EXT_SYC_SLT 0x28
#define ADDR_M_TTCAN_HSM_SW_OVRD 0x2C
#define ADDR_M_TTCAN_TIME_STAMP 0x30
#define M_TTCAN_CNTRL_REG_COK (1<<3)
#define M_TTCAN_TIME_STAMP_OFFSET_SEL 4
#endif /* M_TTCAN_REGDEF_H_ */
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