mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-23 17:55:05 +03:00
7dd632ff96
- support Android-14 - support Linux kernel 6.9 - support 6G regulation - support Thermal protection - support TX shortcut to reduce CPU loading - fix some coverity issues - Use RTW regulatory version rtk_8852CE_M.2_2230-67-52 - default enable con-current and MCC Bug 4667769 Bug 4667981 Change-Id: Iee069ecdd1f00a0b78285d0a4ef5778ed9ace478 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3195601 Tested-by: Shobek Attupurath <sattupurath@nvidia.com> Reviewed-by: Revanth Kumar Uppala <ruppala@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/******************************************************************************
|
|
*
|
|
* Copyright(c) 2021 Realtek Corporation.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of version 2 of the GNU General Public License as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
*****************************************************************************/
|
|
#ifndef _PHL_PS_H_
|
|
#define _PHL_PS_H_
|
|
#ifdef CONFIG_POWER_SAVE
|
|
|
|
#define PS_MACID_NONE 0xFFFF
|
|
|
|
enum phl_ps_ps_int_cfg_step {
|
|
PS_ENTER_CFG_INT_PRE_PHASE,
|
|
PS_ENTER_CFG_INT_POST_PHASE,
|
|
PS_LEAVE_CFG_INT_PRE_PHASE,
|
|
PS_LEAVE_CFG_INT_POST_PHASE,
|
|
PS_LEAVE_CFG_INT_MAX
|
|
};
|
|
|
|
/* use to configure specific pwr mode along with pwr lvl and others */
|
|
struct ps_cfg {
|
|
/* common */
|
|
u8 ps_mode;
|
|
u8 cur_pwr_lvl;
|
|
u8 pwr_lvl;
|
|
u16 macid;
|
|
/* lps */
|
|
bool pwr_cfg; /* whether to configure pwr lvl */
|
|
bool proto_cfg; /* whether to configure protocol */
|
|
u32 *token;
|
|
bool wow;
|
|
u8 listen_bcn_mode;
|
|
u8 awake_interval;
|
|
u8 smart_ps_mode;
|
|
u8 bcnnohit_en;
|
|
u8 lps_force_tx;
|
|
};
|
|
|
|
#define _get_ps_cap(_phl_info) (&_phl_info->phl_com->dev_cap.ps_cap)
|
|
#define _get_ps_sw_cap(_phl_info) (&_phl_info->phl_com->dev_sw_cap.ps_cap)
|
|
|
|
const char *phl_ps_op_mode_to_str(u8 op_mode);
|
|
const char *phl_ps_ps_mode_to_str(u8 ps_mode);
|
|
const char *phl_ps_pwr_lvl_to_str(u8 pwr_lvl);
|
|
u8 phl_ps_judge_pwr_lvl(u8 ps_cap, u8 ps_mode, u8 ps_en);
|
|
|
|
enum rtw_phl_status
|
|
phl_ps_ips_cfg(struct phl_info_t *phl_info, struct ps_cfg *cfg, u8 ips_en);
|
|
enum rtw_phl_status phl_ps_lps_cfg(struct phl_info_t *phl_info, struct ps_cfg *cfg, u8 lps_en);
|
|
enum rtw_phl_status phl_ps_cfg_pwr_lvl(struct phl_info_t *phl_info, u8 ps_mode, u8 cur_pwr_lvl, u8 req_pwr_lvl);
|
|
|
|
enum rtw_phl_status phl_ps_enter_ps(struct phl_info_t *phl_info, struct ps_cfg *cfg);
|
|
enum rtw_phl_status phl_ps_leave_ps(struct phl_info_t *phl_info, struct ps_cfg *cfg);
|
|
|
|
bool phl_ps_sta_in_lps(struct phl_info_t *phl, struct rtw_phl_stainfo_t *sta);
|
|
|
|
void
|
|
phl_ps_sta_ext_trx_nty(struct phl_info_t *phl, u16 macid);
|
|
|
|
#endif
|
|
#endif /* _PHL_PS_H_ */
|