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2aa72a2701
Since the offsets for the tsec engine registers have changed with t264, this change adds the support to use SoC specific register offsets. Jira TSEC-14 Change-Id: I37afc076809008b0948239f5e9555dfa5c763ba8 Signed-off-by: spatki <spatki@nvidia.com> Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3360321 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Nikesh Oswal <noswal@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
62 lines
1.8 KiB
C
62 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Tegra TSEC Module Support
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*/
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#include <vdso/bits.h> /* for BIT(x) macro */
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#include "tsec_regs.h"
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struct tsec_reg_offsets_t t23x_reg_offsets = {
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.QUEUE_HEAD_0 = 0x1c00,
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.QUEUE_TAIL_0 = 0x1c04,
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.MSGQ_HEAD_0 = 0x1c80,
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.MSGQ_TAIL_0 = 0x1c84,
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.EMEMC_0 = 0x1ac0,
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.EMEMD_0 = 0x1ac4,
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.THI_INT_STATUS_0 = 0x78,
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.THI_INT_STATUS_CLR_0 = BIT(0),
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.THI_STREAMID0_0 = 0x30,
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.THI_STREAMID1_0 = 0x34,
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.PRIV_BLOCKER_CTRL_CG1 = 0x1e28,
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.RISCV_CG = 0x2398,
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.RISCV_IRQSCLR_0 = 0x1004,
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.RISCV_IRQSTAT_0 = 0x1008,
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.RISCV_IRQMSET_0 = 0x2520,
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.RISCV_IRQMCLR_0 = 0x2524,
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.RISCV_IRQSCLR_SWGEN0_SET = BIT(6),
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.RISCV_IRQSTAT_SWGEN0 = BIT(6),
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.RISCV_IRQSTAT_SWGEN1 = BIT(7),
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.RISCV_IRQMCLR_SWGEN0_SET = BIT(6),
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.RISCV_IRQMCLR_SWGEN1_SET = BIT(7),
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.RISCV_IRQMSET_SWGEN0_SET = BIT(6),
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.THI_SEC_0 = 0x38,
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.THI_SEC_CHLOCK = BIT(8),
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.RISCV_BCR_CTRL = 0x2668,
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.RISCV_BCR_CTRL_CORE_SELECT_RISCV = BIT(4),
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.RISCV_BCR_DMAADDR_PKCPARAM_LO = 0x2670,
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.RISCV_BCR_DMAADDR_PKCPARAM_HI = 0x2674,
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.RISCV_BCR_DMAADDR_FMCCODE_LO = 0x2678,
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.RISCV_BCR_DMAADDR_FMCCODE_HI = 0x267c,
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.RISCV_BCR_DMAADDR_FMCDATA_LO = 0x2680,
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.RISCV_BCR_DMAADDR_FMCDATA_HI = 0x2684,
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.RISCV_BCR_DMACFG = 0x266c,
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.RISCV_BCR_DMACFG_TARGET_LOCAL_FB = 0x0,
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.RISCV_BCR_DMACFG_LOCK_LOCKED = BIT(31),
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.RISCV_BCR_DMACFG_SEC = 0x2694,
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.RISCV_BCR_DMACFG_SEC_GSCID = 0x1f,
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.FALCON_MAILBOX0 = 0x1040,
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.FALCON_MAILBOX1 = 0x1044,
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.RISCV_CPUCTL = 0x2388,
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.RISCV_CPUCTL_STARTCPU_TRUE = BIT(0),
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.RISCV_CPUCTL_ACTIVE_STAT = 7,
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.RISCV_CPUCTL_ACTIVE_STAT_ACTIVE = 1,
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.RISCV_BR_RETCODE = 0x265c,
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.RISCV_BR_RETCODE_RESULT = 0,
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.RISCV_BR_RETCODE_RESULT_PASS = 0x3,
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.FALCON_DMEMC_0 = 0x11c0,
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.FALCON_DMEMD_0 = 0x11c4,
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.DMEM_LOGBUF_OFFSET = 0x14000,
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};
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