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2f69bee627
- Updates licenses for DCE-KMD files that are shared with HVRTOS.
- Update from GPL-2.0 to MIT as we use these files in both
open source and closed source context.
JIRA TDS-16741
Change-Id: Icf7aeb737f2f3b294bb9ff9c36d5ed7220c13dea
Signed-off-by: anupamg <anupamg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3293404
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
127 lines
4.7 KiB
C
127 lines
4.7 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2016-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef DCE_INTERFACE_H
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#define DCE_INTERFACE_H
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#include <interface/dce-bitops.h>
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/*
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* XXX: TODO
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*
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* These should be defined in terms of the HW registers
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*/
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#define DCE_NUM_SEMA_REGS 4
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#define DCE_NUM_MBOX_REGS 8
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/*
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* Symbolic definitions of the semaphore registers
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*/
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typedef uint32_t hsp_sema_t;
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#define DCE_BOOT_SEMA (hsp_sema_t)0U
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/*
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* Definitions for DCE_BOOT_SEMA
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*
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* Used to communicate bits of information between the OS and DCE
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*/
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/*
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* Bits set by the OS and examined by the R5
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*/
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#define DCE_BOOT_INT DCE_BIT(31) // interrupt when DCE is ready
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#define DCE_WAIT_DEBUG DCE_BIT(30) // wait in debug loop
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#define DCE_SC7_RESUME DCE_BIT(29) // resume using saved SC7 state
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// rather than a full restart
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#define DCE_OS_BITMASK (DCE_BOOT_INT | DCE_WAIT_DEBUG | DCE_SC7_RESUME)
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/*
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* Bits set by the R5 and examined by the OS
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*/
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#define DCE_BOOT_TCM_COPY DCE_BIT(15) // uCode has copied to TCM
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#define DCE_BOOT_HW_INIT DCE_BIT(14) // hardware init complete
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#define DCE_BOOT_MPU_INIT DCE_BIT(13) // MPU initialized
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#define DCE_BOOT_CACHE_INIT DCE_BIT(12) // cache initialized
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#define DCE_BOOT_R5_INIT DCE_BIT(11) // R5 initialized
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#define DCE_BOOT_DRIVER_INIT DCE_BIT(10) // driver init complete
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#define DCE_BOOT_MAIN_STARTED DCE_BIT(9) // main started
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#define DCE_BOOT_TASK_INIT_START DCE_BIT(8) // task initialization started
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#define DCE_BOOT_TASK_INIT_DONE DCE_BIT(7) // task initialization complete
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#define DCE_HALTED DCE_BIT(1) // uCode has halted
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#define DCE_BOOT_COMPLETE DCE_BIT(0) // uCode boot has completed
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/*
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* Symbolic definitions of the doorbell registers
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*/
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typedef uint32_t hsp_db_t;
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/*
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* Symbolic definitions of the mailbox registers (rather than using 0-7)
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*/
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typedef uint32_t hsp_mbox_t;
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#define DCE_MBOX_FROM_DCE_RM (hsp_mbox_t)0U // signal from RM IPC
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#define DCE_MBOX_TO_DCE_RM (hsp_mbox_t)1U // signal to RM IPC
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#define DCE_MBOX_FROM_DCE_RM_EVENT_NOTIFY (hsp_mbox_t)2U // signal to DCE for event notification
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#define DCE_MBOX_TO_DCE_RM_EVENT_NOTIFY (hsp_mbox_t)3U // signal from DCE for event notification IPC
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#define DCE_MBOX_FROM_DCE_ADMIN (hsp_mbox_t)4U // signal from DCE ADMIN IPC
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#define DCE_MBOX_TO_DCE_ADMIN (hsp_mbox_t)5U // signal to ADMIN IPC
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#define DCE_MBOX_BOOT_CMD (hsp_mbox_t)6U // boot commands
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#define DCE_MBOX_IRQ (hsp_mbox_t)7U // general interrupt/status
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/*
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* Generic interrupts & status from the DCE are reported in DCE_MBOX_IRQ
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*/
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#define DCE_IRQ_PENDING DCE_BIT(31)// interrupt is pending
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#define DCE_IRQ_GET_STATUS_TYPE(_x_) DCE_EXTRACT(_x_, 30, 27, uint32_t)
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#define DCE_IRQ_SET_STATUS_TYPE(_x_) DCE_INSERT(0U, 30, 27, _x_)
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#define DCE_IRQ_STATUS_TYPE_IRQ 0x0 // irq status
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#define DCE_IRQ_STATUS_TYPE_BOOT_CMD 0x1 // boot command status
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#define NUM_DCE_IRQ_STATUS_TYPES 2
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#define DCE_IRQ_GET_STATUS(_x_) DCE_EXTRACT(_x_, 23, 0, uint32_t)
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#define DCE_IRQ_SET_STATUS(_x_) DCE_INSERT(0U, 23, 0, _x_)
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/*
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* Bits in status field when IRQ_STATUS_TYPE == IRQ_STATUS_TYPE_IRQ
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*/
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#define DCE_IRQ_READY DCE_BIT(23) // DCE is ready
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#define DCE_IRQ_LOG_OVERFLOW DCE_BIT(22) // trace log overflow
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#define DCE_IRQ_LOG_READY DCE_BIT(21) // trace log buffers available
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#define DCE_IRQ_CRASH_LOG DCE_BIT(20) // crash log available
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#define DCE_IRQ_ABORT DCE_BIT(19) // uCode abort occurred
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#define DCE_IRQ_SC7_ENTERED DCE_BIT(18) // DCE state saved
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// can be powered off
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/*
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* MBOX contents for IPC are the same for all of the mailboxes that are
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* used for signaling IPC. Not all values will be useful for all mailboxes.
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*/
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#define DCE_IPC_IRQ_PENDING DCE_BIT(31) // interrupt is pending
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#endif
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