Rakesh Goyal 30a6d63eb2 nvethernet: read pps output freq control ...

Issue: Default 1 pulse (of width clk_ptp_ref_i) every
second.

Fix: The binary rollover is 2 Hz, and the digital
rollover is 1 Hz. low period of 537 ms and a high
period of 463 ms.

Bug 3462227

Change-Id: I5ec433af9e64e7709ba8e3d01261fe8a29d83198
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2641897
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2022-11-01 14:27:08 +05:30

..

nvidia

nvethernet: read pps output freq control

2022-11-01 14:27:08 +05:30

Makefile

net: ethernet: nvidia: add pcie vnet driver

2022-07-05 14:32:20 -07:00