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33a40367c0
Move from the old, complex intr handling code to a new implementation based on dma_fences. While there is a fair bit of churn to get there, the new implementation is much simpler and likely faster as well due to allowing signaling directly from interrupt context. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Change-Id: I81c47fa1946679813f90e3fd8e1d1e9d6342143e Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2786635 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
30 lines
468 B
C
30 lines
468 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020, NVIDIA Corporation.
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*/
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#ifndef HOST1X_FENCE_H
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#define HOST1X_FENCE_H
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struct host1x_syncpt_fence {
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struct dma_fence base;
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atomic_t signaling;
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struct host1x_syncpt *sp;
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u32 threshold;
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struct delayed_work timeout_work;
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struct list_head list;
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};
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struct host1x_fence_list {
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spinlock_t lock;
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struct list_head list;
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};
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void host1x_fence_signal(struct host1x_syncpt_fence *fence);
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#endif
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