mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
synced 2025-12-24 10:11:26 +03:00
34b3cc18d3
fixes for: a) asrc b) arad c) machine driver List of CL's: http://git-master/r/799350 http://git-master/r/799941 http://git-master/r/801101 Bug 200133225 Change-Id: Icbec3b988e134c47dc13cbf64bbef394bc31b0a6 Signed-off-by: Dipesh Gandhi <dipeshg@nvidia.com> Reviewed-on: http://git-master/r/823283 Reviewed-by: Sharad Gupta <sharadg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nitin Pai <npai@nvidia.com>
878 lines
27 KiB
C
878 lines
27 KiB
C
/*
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* tegra186_arad_alt.c - Tegra186 ARAD driver
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*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/irqchip/tegra-agic.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/of_device.h>
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#include "tegra186_asrc_alt.h"
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#include "tegra210_xbar_alt.h"
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#include "tegra186_arad_alt.h"
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#define DRV_NAME "tegra186-arad"
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#define ARAD_LANE_NUMERATOR_MUX(id) \
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(TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL + id*TEGRA186_ARAD_LANE_STRIDE)
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#define ARAD_LANE_DENOMINATOR_MUX(id) \
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(TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL + id*TEGRA186_ARAD_LANE_STRIDE)
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#define ARAD_LANE_REG(reg, id) (reg + (id * TEGRA186_ARAD_LANE_STRIDE))
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#define ASRC_STREAM_REG_DEFAULTS(id) \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_RATIO_INTEGER_PART, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_RATIO_FRACTIONAL_PART, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_NUMERATOR_PRESCALAR, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_DENOMINATOR_PRESCALAR, id), 0x0}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_SERVO_LOOP_CONFIG, id), 0xd5e7}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_LOCK_UNLOCK_DETECTOR_CONFIG, id), 0x840500}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_ERROR_LOCK_THRESHOLD, id), 0x400000}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_ERROR_UNLOCK_THRESHOLD, id), 0xa00000}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_RATIO_CALCULATOR_CONFIG, id), 0xf000006}, \
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{ ARAD_LANE_REG(TEGRA186_ARAD_LANE1_CYA, id), 0x0}
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static const struct reg_default tegra186_arad_reg_defaults[] = {
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{ TEGRA186_ARAD_LANE_ENABLE, 0x0},
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{ TEGRA186_ARAD_LANE_SOFT_RESET, 0x0},
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{ TEGRA186_ARAD_LANE_INT_MASK, 0x0},
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{ TEGRA186_ARAD_LANE_INT_SET, 0x0},
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{ TEGRA186_ARAD_LANE_INT_CLEAR, 0x0},
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{ TEGRA186_ARAD_LANE_INT_CLEAR, 0x0},
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{ TEGRA186_ARAD_CG, 0x0},
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{ TEGRA186_ARAD_CYA_GLOBAL, 0x0},
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ASRC_STREAM_REG_DEFAULTS(0),
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ASRC_STREAM_REG_DEFAULTS(1),
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ASRC_STREAM_REG_DEFAULTS(2),
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ASRC_STREAM_REG_DEFAULTS(3),
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ASRC_STREAM_REG_DEFAULTS(4),
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ASRC_STREAM_REG_DEFAULTS(5),
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{ TEGRA186_ARAD_TX_CIF_CTRL, 0x115500},
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};
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static int tegra186_arad_runtime_suspend(struct device *dev)
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{
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struct tegra186_arad *arad = dev_get_drvdata(dev);
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regcache_cache_only(arad->regmap, true);
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pm_runtime_put_sync(dev->parent);
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return 0;
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}
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static int tegra186_arad_runtime_resume(struct device *dev)
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{
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struct tegra186_arad *arad = dev_get_drvdata(dev);
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int ret;
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ret = pm_runtime_get_sync(dev->parent);
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if (ret < 0) {
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dev_err(dev, "parent get_sync failed: %d\n", ret);
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return ret;
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}
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regcache_cache_only(arad->regmap, false);
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regcache_sync(arad->regmap);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra186_arad_suspend(struct device *dev)
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{
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struct tegra186_arad *arad = dev_get_drvdata(dev);
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regcache_mark_dirty(arad->regmap);
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return 0;
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}
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#endif
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static int tegra186_arad_codec_probe(struct snd_soc_codec *codec)
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{
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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codec->control_data = arad->regmap;
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return 0;
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}
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static int tegra186_arad_get_lane_lock_status(
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struct tegra186_arad *arad, unsigned int lane_id)
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{
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unsigned int val;
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regmap_read(arad->regmap,
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TEGRA186_ARAD_LANE_STATUS, &val);
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val = (val >> (16 + lane_id)) & 0x1;
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return val;
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}
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static int tegra186_arad_get_lane_ratio_change_status(
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struct tegra186_arad *arad, unsigned int lane_id)
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{
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unsigned int val;
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regmap_read(arad->regmap,
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TEGRA186_ARAD_LANE_INT_STATUS, &val);
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val = (val >> (16 + lane_id)) & 0x1;
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return val;
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}
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static struct snd_soc_dai_ops tegra186_arad_out_dai_ops = {
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};
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static struct snd_soc_dai_driver tegra186_arad_dais[] = {
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{
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.name = "ARAD OUT",
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.capture = {
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.stream_name = "ARAD Transmit",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S24_LE,
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},
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.ops = &tegra186_arad_out_dai_ops,
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},
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};
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static const int tegra186_arad_mux_value[] = {
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-1, /* None */
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0, 1, 2, 3, 4, 5, /* I2S1~6 */
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12, 13, 14, 15, /* DMIC1~4 */
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24, 25, /* DSPK1~2 */
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26, 27, /* IQC1~2 */
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28, 29, 30, 31, /* SPDIF_RX1,2 & SPDIF_TX1,2 */
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};
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static const char * const tegra186_arad_mux_text[] = {
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"None",
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"I2S1",
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"I2S2",
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"I2S3",
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"I2S4",
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"I2S5",
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"I2S6",
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"DMIC1",
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"DMIC2",
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"DMIC3",
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"DMIC4",
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"DSPK1",
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"DSPK2",
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"IQC1",
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"IQC2",
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"SPDIF1_RX1",
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"SPDIF1_RX2",
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"SPDIF1_TX1",
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"SPDIF1_TX2",
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};
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static int tegra186_arad_mux_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_enum *arad_private =
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(struct soc_enum *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int val, loop = 0;
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regmap_read(arad->regmap, arad_private->reg, &val);
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if (val) {
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for (loop = 1; loop < 19; loop++)
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if (val & (1<<arad_private->values[loop])) {
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val = loop;
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break;
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}
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}
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ucontrol->value.integer.value[0] = val;
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return 0;
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}
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static int tegra186_arad_mux_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_enum *arad_private =
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(struct soc_enum *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int val = ucontrol->value.integer.value[0];
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if (!val)
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regmap_write(arad->regmap, arad_private->reg, 0);
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else
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regmap_write(arad->regmap, arad_private->reg,
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1 << arad_private->values[val]);
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return 0;
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}
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static int tegra186_arad_get_ratio_int(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *arad_private =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int val;
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regmap_read(arad->regmap, arad_private->reg, &val);
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ucontrol->value.integer.value[0] = val;
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return 0;
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}
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static int tegra186_arad_get_ratio_frac(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *arad_private =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int val;
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regmap_read(arad->regmap, arad_private->reg, &val);
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ucontrol->value.integer.value[0] = val;
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return 0;
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}
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static int tegra186_arad_get_enable_lane(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *arad_private =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int enable;
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regmap_read(arad->regmap, arad_private->reg, &enable);
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enable = (enable >> arad_private->shift) & arad_private->max;
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ucontrol->value.integer.value[0] = enable;
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return 0;
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}
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static int tegra186_arad_put_enable_lane(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *arad_private =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
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struct tegra186_arad *arad = snd_soc_codec_get_drvdata(codec);
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unsigned int enable = 0, lane_id = arad_private->shift;
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int dcnt = 10;
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enable = ucontrol->value.integer.value[0];
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regmap_update_bits(arad->regmap,
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arad_private->reg, 1<<arad_private->shift,
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enable<<arad_private->shift);
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#ifdef CONFIG_SND_SOC_TEGRA186_ARAD_WAR
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regmap_update_bits(arad->regmap,
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TEGRA186_ARAD_LANE_INT_MASK,
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1<<(TEGRA186_ARAD_LANE_INT_RATIO_CHANGE_SHIFT + lane_id),
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1<<(TEGRA186_ARAD_LANE_INT_RATIO_CHANGE_SHIFT + lane_id));
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#endif
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if (enable)
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while (!tegra186_arad_get_lane_lock_status(arad, lane_id) &&
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dcnt--)
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udelay(100);
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else {
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regmap_update_bits(arad->regmap,
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TEGRA186_ARAD_LANE_SOFT_RESET, 1<<arad_private->shift,
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1<<arad_private->shift);
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while (tegra186_arad_get_lane_lock_status(arad, lane_id) &&
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dcnt--)
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udelay(100);
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}
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if (dcnt < 0) {
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if (enable)
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pr_err("ARAD Lane %d can't be locked\n", lane_id+1);
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else
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pr_err("ARAD Lane %d can't be unlocked\n", lane_id+1);
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return -ETIMEDOUT;
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} else
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return 0;
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}
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#define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues) \
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{ .reg = xreg, .shift_l = shift, .shift_r = shift, \
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.items = xmax, .texts = xtexts, .values = xvalues, \
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.mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0}
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#define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, \
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xtexts, xvalues) \
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struct soc_enum name = SOC_VALUE_ENUM_WIDE(xreg, shift, \
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ARRAY_SIZE(xtexts), xtexts, xvalues)
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#define ARAD_MUX_ENUM_CTRL_DECL(ename, reg) \
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SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, reg, 0, \
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tegra186_arad_mux_text, tegra186_arad_mux_value); \
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static const struct snd_kcontrol_new ename##_ctrl = \
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SOC_DAPM_ENUM_EXT("Mux", ename##_enum, \
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tegra186_arad_mux_get, \
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tegra186_arad_mux_put)
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static ARAD_MUX_ENUM_CTRL_DECL(numerator1,
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TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(numerator2,
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TEGRA186_ARAD_LANE2_NUMERATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(numerator3,
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TEGRA186_ARAD_LANE3_NUMERATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(numerator4,
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TEGRA186_ARAD_LANE4_NUMERATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(numerator5,
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TEGRA186_ARAD_LANE5_NUMERATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(numerator6,
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TEGRA186_ARAD_LANE6_NUMERATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(denominator1,
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TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(denominator2,
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TEGRA186_ARAD_LANE2_DENOMINATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(denominator3,
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TEGRA186_ARAD_LANE3_DENOMINATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(denominator4,
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TEGRA186_ARAD_LANE4_DENOMINATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(denominator5,
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TEGRA186_ARAD_LANE5_DENOMINATOR_MUX_SEL);
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static ARAD_MUX_ENUM_CTRL_DECL(denominator6,
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TEGRA186_ARAD_LANE6_DENOMINATOR_MUX_SEL);
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#define ARAD_RATIO_GEN_WIDGETS(sname, ename) \
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SND_SOC_DAPM_AIF_OUT(sname " TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
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SND_SOC_DAPM_MUX(sname " MUX", SND_SOC_NOPM, 0, 0, &ename##_ctrl)
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static const struct snd_soc_dapm_widget tegra186_arad_widgets[] = {
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SND_SOC_DAPM_SIGGEN("I2S1 SIG"),
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SND_SOC_DAPM_SIGGEN("I2S2 SIG"),
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SND_SOC_DAPM_SIGGEN("I2S3 SIG"),
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SND_SOC_DAPM_SIGGEN("I2S4 SIG"),
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SND_SOC_DAPM_SIGGEN("I2S5 SIG"),
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SND_SOC_DAPM_SIGGEN("I2S6 SIG"),
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SND_SOC_DAPM_SIGGEN("DMIC1 SIG"),
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SND_SOC_DAPM_SIGGEN("DMIC2 SIG"),
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SND_SOC_DAPM_SIGGEN("DMIC3 SIG"),
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SND_SOC_DAPM_SIGGEN("DMIC4 SIG"),
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SND_SOC_DAPM_SIGGEN("DSPK1 SIG"),
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SND_SOC_DAPM_SIGGEN("DSPK2 SIG"),
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SND_SOC_DAPM_SIGGEN("IQC1 SIG"),
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SND_SOC_DAPM_SIGGEN("IQC2 SIG"),
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SND_SOC_DAPM_SIGGEN("SPDIF1_RX1 SIG"),
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SND_SOC_DAPM_SIGGEN("SPDIF1_RX2 SIG"),
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SND_SOC_DAPM_SIGGEN("SPDIF1_TX1 SIG"),
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SND_SOC_DAPM_SIGGEN("SPDIF1_TX2 SIG"),
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ARAD_RATIO_GEN_WIDGETS("Numerator1", numerator1),
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ARAD_RATIO_GEN_WIDGETS("Numerator2", numerator2),
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ARAD_RATIO_GEN_WIDGETS("Numerator3", numerator3),
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ARAD_RATIO_GEN_WIDGETS("Numerator4", numerator4),
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ARAD_RATIO_GEN_WIDGETS("Numerator5", numerator5),
|
|
ARAD_RATIO_GEN_WIDGETS("Numerator6", numerator6),
|
|
ARAD_RATIO_GEN_WIDGETS("Denominator1", denominator1),
|
|
ARAD_RATIO_GEN_WIDGETS("Denominator2", denominator2),
|
|
ARAD_RATIO_GEN_WIDGETS("Denominator3", denominator3),
|
|
ARAD_RATIO_GEN_WIDGETS("Denominator4", denominator4),
|
|
ARAD_RATIO_GEN_WIDGETS("Denominator5", denominator5),
|
|
ARAD_RATIO_GEN_WIDGETS("Denominator6", denominator6),
|
|
|
|
SND_SOC_DAPM_AIF_OUT("Packetizer", NULL, 0, 0, 0, 0),
|
|
};
|
|
|
|
#define RATIO_GEN_ROUTE(sname) \
|
|
{ sname " MUX", NULL, "I2S1 SIG" }, \
|
|
{ sname " MUX", NULL, "I2S2 SIG" }, \
|
|
{ sname " MUX", NULL, "I2S3 SIG" }, \
|
|
{ sname " MUX", NULL, "I2S4 SIG" }, \
|
|
{ sname " MUX", NULL, "I2S5 SIG" }, \
|
|
{ sname " MUX", NULL, "I2S6 SIG" }, \
|
|
{ sname " MUX", NULL, "DMIC1 SIG" }, \
|
|
{ sname " MUX", NULL, "DMIC2 SIG" }, \
|
|
{ sname " MUX", NULL, "DMIC3 SIG" }, \
|
|
{ sname " MUX", NULL, "DMIC4 SIG" }, \
|
|
{ sname " MUX", NULL, "IQC1 SIG" }, \
|
|
{ sname " MUX", NULL, "IQC2 SIG" }, \
|
|
{ sname " MUX", NULL, "SPDIF1_RX1 SIG" }, \
|
|
{ sname " MUX", NULL, "SPDIF1_RX2 SIG" }, \
|
|
{ sname " MUX", NULL, "SPDIF1_TX1 SIG" }, \
|
|
{ sname " MUX", NULL, "SPDIF1_TX2 SIG" }
|
|
|
|
#define RATIO_GEN(sname) \
|
|
RATIO_GEN_ROUTE(sname), \
|
|
{ sname " TX", NULL, sname " MUX" }
|
|
|
|
#define PACKETIZER_ROUTE(sname) \
|
|
{ sname, "Numerator1 TX", "Numerator1 TX" }, \
|
|
{ sname, "Numerator2 TX", "Numerator2 TX" }, \
|
|
{ sname, "Numerator3 TX", "Numerator3 TX" }, \
|
|
{ sname, "Numerator4 TX", "Numerator4 TX" }, \
|
|
{ sname, "Numerator5 TX", "Numerator5 TX" }, \
|
|
{ sname, "Numerator6 TX", "Numerator6 TX" }, \
|
|
{ sname, "Denominator1 TX", "Denominator1 TX" }, \
|
|
{ sname, "Denominator2 TX", "Denominator2 TX" }, \
|
|
{ sname, "Denominator3 TX", "Denominator3 TX" }, \
|
|
{ sname, "Denominator4 TX", "Denominator4 TX" }, \
|
|
{ sname, "Denominator5 TX", "Denominator5 TX" }, \
|
|
{ sname, "Denominator6 TX", "Denominator6 TX" }
|
|
|
|
static const struct snd_soc_dapm_route tegra186_arad_routes[] = {
|
|
RATIO_GEN("Numerator1"),
|
|
RATIO_GEN("Numerator2"),
|
|
RATIO_GEN("Numerator3"),
|
|
RATIO_GEN("Numerator4"),
|
|
RATIO_GEN("Numerator5"),
|
|
RATIO_GEN("Numerator6"),
|
|
RATIO_GEN("Denominator1"),
|
|
RATIO_GEN("Denominator2"),
|
|
RATIO_GEN("Denominator3"),
|
|
RATIO_GEN("Denominator4"),
|
|
RATIO_GEN("Denominator5"),
|
|
RATIO_GEN("Denominator6"),
|
|
|
|
PACKETIZER_ROUTE("Packetizer"),
|
|
|
|
{ "ARAD Transmit", NULL, "Packetizer" },
|
|
};
|
|
|
|
static const struct snd_kcontrol_new tegra186_arad_controls[] = {
|
|
SOC_SINGLE_EXT("Lane1 enable", TEGRA186_ARAD_LANE_ENABLE, 0, 1, 0,
|
|
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
|
SOC_SINGLE_EXT("Lane2 enable", TEGRA186_ARAD_LANE_ENABLE, 1, 1, 0,
|
|
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
|
SOC_SINGLE_EXT("Lane3 enable", TEGRA186_ARAD_LANE_ENABLE, 2, 1, 0,
|
|
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
|
SOC_SINGLE_EXT("Lane4 enable", TEGRA186_ARAD_LANE_ENABLE, 3, 1, 0,
|
|
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
|
SOC_SINGLE_EXT("Lane5 enable", TEGRA186_ARAD_LANE_ENABLE, 4, 1, 0,
|
|
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
|
SOC_SINGLE_EXT("Lane6 enable", TEGRA186_ARAD_LANE_ENABLE, 5, 1, 0,
|
|
tegra186_arad_get_enable_lane, tegra186_arad_put_enable_lane),
|
|
|
|
SOC_SINGLE_EXT("Lane1 Ratio Int",
|
|
TEGRA186_ARAD_LANE1_RATIO_INTEGER_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_int, NULL),
|
|
SOC_SINGLE_EXT("Lane1 Ratio Frac",
|
|
TEGRA186_ARAD_LANE1_RATIO_FRACTIONAL_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_frac, NULL),
|
|
SOC_SINGLE_EXT("Lane2 Ratio Int",
|
|
TEGRA186_ARAD_LANE2_RATIO_INTEGER_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_int, NULL),
|
|
SOC_SINGLE_EXT("Lane2 Ratio Frac",
|
|
TEGRA186_ARAD_LANE2_RATIO_FRACTIONAL_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_frac, NULL),
|
|
SOC_SINGLE_EXT("Lane3 Ratio Int",
|
|
TEGRA186_ARAD_LANE3_RATIO_INTEGER_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_int, NULL),
|
|
SOC_SINGLE_EXT("Lane3 Ratio Frac",
|
|
TEGRA186_ARAD_LANE3_RATIO_FRACTIONAL_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_frac, NULL),
|
|
SOC_SINGLE_EXT("Lane4 Ratio Int",
|
|
TEGRA186_ARAD_LANE4_RATIO_INTEGER_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_int, NULL),
|
|
SOC_SINGLE_EXT("Lane4 Ratio Frac",
|
|
TEGRA186_ARAD_LANE4_RATIO_FRACTIONAL_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_frac, NULL),
|
|
SOC_SINGLE_EXT("Lane5 Ratio Int",
|
|
TEGRA186_ARAD_LANE5_RATIO_INTEGER_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_int, NULL),
|
|
SOC_SINGLE_EXT("Lane5 Ratio Frac",
|
|
TEGRA186_ARAD_LANE5_RATIO_FRACTIONAL_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_frac, NULL),
|
|
SOC_SINGLE_EXT("Lane6 Ratio Int",
|
|
TEGRA186_ARAD_LANE6_RATIO_INTEGER_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_INTEGER_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_int, NULL),
|
|
SOC_SINGLE_EXT("Lane6 Ratio Frac",
|
|
TEGRA186_ARAD_LANE6_RATIO_FRACTIONAL_PART,
|
|
0, TEGRA186_ARAD_LANE_RATIO_FRAC_PART_MASK, 0,
|
|
tegra186_arad_get_ratio_frac, NULL),
|
|
};
|
|
|
|
static struct snd_soc_codec_driver tegra186_arad_codec = {
|
|
.probe = tegra186_arad_codec_probe,
|
|
.dapm_widgets = tegra186_arad_widgets,
|
|
.num_dapm_widgets = ARRAY_SIZE(tegra186_arad_widgets),
|
|
.dapm_routes = tegra186_arad_routes,
|
|
.num_dapm_routes = ARRAY_SIZE(tegra186_arad_routes),
|
|
.controls = tegra186_arad_controls,
|
|
.num_controls = ARRAY_SIZE(tegra186_arad_controls),
|
|
.idle_bias_off = 1,
|
|
};
|
|
|
|
static bool tegra186_arad_wr_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
if ((reg >= TEGRA186_ARAD_LANE_START) &&
|
|
(reg <= TEGRA186_ARAD_LANE_LIMIT)) {
|
|
reg -= TEGRA186_ARAD_LANE_START;
|
|
reg %= TEGRA186_ARAD_LANE_STRIDE;
|
|
reg += TEGRA186_ARAD_LANE_START;
|
|
}
|
|
|
|
switch (reg) {
|
|
case TEGRA186_ARAD_LANE_ENABLE:
|
|
case TEGRA186_ARAD_LANE_SOFT_RESET:
|
|
case TEGRA186_ARAD_LANE_INT_MASK:
|
|
case TEGRA186_ARAD_LANE_INT_SET:
|
|
case TEGRA186_ARAD_LANE_INT_CLEAR:
|
|
case TEGRA186_ARAD_GLOBAL_SOFT_RESET:
|
|
case TEGRA186_ARAD_SEND_RATIO:
|
|
case TEGRA186_ARAD_CG:
|
|
case TEGRA186_ARAD_CYA_GLOBAL:
|
|
|
|
case TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL:
|
|
case TEGRA186_ARAD_LANE1_NUMERATOR_PRESCALAR:
|
|
case TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL:
|
|
case TEGRA186_ARAD_LANE1_DENOMINATOR_PRESCALAR:
|
|
case TEGRA186_ARAD_LANE1_SERVO_LOOP_CONFIG:
|
|
case TEGRA186_ARAD_LANE1_LOCK_UNLOCK_DETECTOR_CONFIG:
|
|
case TEGRA186_ARAD_LANE1_ERROR_LOCK_THRESHOLD:
|
|
case TEGRA186_ARAD_LANE1_ERROR_UNLOCK_THRESHOLD:
|
|
case TEGRA186_ARAD_LANE1_RATIO_CALCULATOR_CONFIG:
|
|
case TEGRA186_ARAD_LANE1_CYA:
|
|
return true;
|
|
default:
|
|
return false;
|
|
};
|
|
}
|
|
|
|
static bool tegra186_arad_rd_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
if ((reg >= TEGRA186_ARAD_LANE_START) &&
|
|
(reg <= TEGRA186_ARAD_LANE_LIMIT)) {
|
|
reg -= TEGRA186_ARAD_LANE_START;
|
|
reg %= TEGRA186_ARAD_LANE_STRIDE;
|
|
reg += TEGRA186_ARAD_LANE_START;
|
|
}
|
|
|
|
switch (reg) {
|
|
case TEGRA186_ARAD_LANE_ENABLE:
|
|
case TEGRA186_ARAD_LANE_STATUS:
|
|
case TEGRA186_ARAD_LANE_SOFT_RESET:
|
|
case TEGRA186_ARAD_LANE_INT_STATUS:
|
|
case TEGRA186_ARAD_LANE_INT_MASK:
|
|
case TEGRA186_ARAD_LANE_INT_SET:
|
|
case TEGRA186_ARAD_LANE_INT_CLEAR:
|
|
case TEGRA186_ARAD_GLOBAL_SOFT_RESET:
|
|
case TEGRA186_ARAD_CG:
|
|
case TEGRA186_ARAD_STATUS:
|
|
case TEGRA186_ARAD_CYA_GLOBAL:
|
|
|
|
case TEGRA186_ARAD_LANE1_NUMERATOR_MUX_SEL:
|
|
case TEGRA186_ARAD_LANE1_NUMERATOR_PRESCALAR:
|
|
case TEGRA186_ARAD_LANE1_DENOMINATOR_MUX_SEL:
|
|
case TEGRA186_ARAD_LANE1_DENOMINATOR_PRESCALAR:
|
|
case TEGRA186_ARAD_LANE1_RATIO_INTEGER_PART:
|
|
case TEGRA186_ARAD_LANE1_RATIO_FRACTIONAL_PART:
|
|
case TEGRA186_ARAD_LANE1_PERIOD_COUNT:
|
|
case TEGRA186_ARAD_LANE1_SERVO_LOOP_CONFIG:
|
|
case TEGRA186_ARAD_LANE1_LOCK_UNLOCK_DETECTOR_CONFIG:
|
|
case TEGRA186_ARAD_LANE1_ERROR_LOCK_THRESHOLD:
|
|
case TEGRA186_ARAD_LANE1_ERROR_UNLOCK_THRESHOLD:
|
|
case TEGRA186_ARAD_LANE1_RATIO_CALCULATOR_CONFIG:
|
|
case TEGRA186_ARAD_LANE1_CYA:
|
|
return true;
|
|
default:
|
|
return false;
|
|
};
|
|
}
|
|
|
|
static bool tegra186_arad_volatile_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
if ((reg >= TEGRA186_ARAD_LANE_START) &&
|
|
(reg <= TEGRA186_ARAD_LANE_LIMIT)) {
|
|
reg -= TEGRA186_ARAD_LANE_START;
|
|
reg %= TEGRA186_ARAD_LANE_STRIDE;
|
|
reg += TEGRA186_ARAD_LANE_START;
|
|
}
|
|
|
|
switch (reg) {
|
|
case TEGRA186_ARAD_LANE_STATUS:
|
|
case TEGRA186_ARAD_LANE_INT_STATUS:
|
|
case TEGRA186_ARAD_STATUS:
|
|
|
|
case TEGRA186_ARAD_LANE1_RATIO_INTEGER_PART:
|
|
case TEGRA186_ARAD_LANE1_RATIO_FRACTIONAL_PART:
|
|
case TEGRA186_ARAD_LANE1_PERIOD_COUNT:
|
|
return true;
|
|
default:
|
|
return false;
|
|
};
|
|
}
|
|
|
|
static const struct regmap_config tegra186_arad_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = TEGRA186_ARAD_TX_CIF_CTRL,
|
|
.writeable_reg = tegra186_arad_wr_reg,
|
|
.readable_reg = tegra186_arad_rd_reg,
|
|
.volatile_reg = tegra186_arad_volatile_reg,
|
|
.reg_defaults = tegra186_arad_reg_defaults,
|
|
.num_reg_defaults = ARRAY_SIZE(tegra186_arad_reg_defaults),
|
|
.cache_type = REGCACHE_FLAT,
|
|
};
|
|
|
|
static const struct tegra186_arad_soc_data soc_data_tegra186 = {
|
|
.set_audio_cif = tegra210_xbar_set_cif,
|
|
};
|
|
|
|
static const struct of_device_id tegra186_arad_of_match[] = {
|
|
{ .compatible = "nvidia,tegra186-arad", .data = &soc_data_tegra186 },
|
|
{},
|
|
};
|
|
|
|
#ifdef CONFIG_SND_SOC_TEGRA186_ARAD_WAR
|
|
static irqreturn_t tegra186_arad_interrupt_handler(int irq, void *data)
|
|
{
|
|
unsigned long flags;
|
|
int i = 0, inte = 0, frac = 0;
|
|
unsigned int status = 0, val = 0;
|
|
struct tegra186_arad *arad = dev_get_drvdata(
|
|
(struct device *) data);
|
|
|
|
spin_lock_irqsave(&arad->int_lock, flags);
|
|
/* WAR for Bug 200102368 */
|
|
regmap_read(arad->regmap,
|
|
TEGRA186_ARAD_LANE_INT_STATUS, &status);
|
|
for (i = 0; i < TEGRA186_ARAD_LANE_MAX; i++) {
|
|
if ((1 << i) & status) {
|
|
|
|
regmap_read(arad->regmap,
|
|
TEGRA186_ARAD_LANE_ENABLE, &val);
|
|
val |= 1<<i;
|
|
|
|
regmap_write(arad->regmap,
|
|
TEGRA186_ARAD_LANE_INT_CLEAR, 1<<i);
|
|
regmap_write(arad->regmap,
|
|
TEGRA186_ARAD_LANE_SOFT_RESET, 1<<i);
|
|
regmap_write(arad->regmap,
|
|
TEGRA186_ARAD_LANE_ENABLE, val);
|
|
#ifdef CONFIG_SND_SOC_TEGRA186_ASRC_WAR
|
|
tegra186_asrc_event(i, STREAM_DISABLE, 0);
|
|
#endif
|
|
/* In case ratio change is masked becasue of
|
|
previous locking, unmask it*/
|
|
regmap_update_bits(arad->regmap,
|
|
TEGRA186_ARAD_LANE_INT_MASK,
|
|
1<<(TEGRA186_ARAD_LANE_INT_RATIO_CHANGE_SHIFT
|
|
+ i), 0);
|
|
val = 0;
|
|
} /*
|
|
Its a case where interrupt is because of
|
|
ratio change, to offload unecessary interrupt
|
|
handling in locked state mask ratio change
|
|
interrupt */
|
|
else if (tegra186_arad_get_lane_lock_status(arad, i) &&
|
|
tegra186_arad_get_lane_ratio_change_status(arad, i)) {
|
|
|
|
regmap_update_bits(arad->regmap,
|
|
TEGRA186_ARAD_LANE_INT_MASK,
|
|
1<<(TEGRA186_ARAD_LANE_INT_RATIO_CHANGE_SHIFT + i),
|
|
1<<(TEGRA186_ARAD_LANE_INT_RATIO_CHANGE_SHIFT+i));
|
|
|
|
regmap_write(arad->regmap,
|
|
TEGRA186_ARAD_LANE_INT_CLEAR,
|
|
1<<(TEGRA186_ARAD_LANE_INT_RATIO_CHANGE_SHIFT+i));
|
|
|
|
#ifdef CONFIG_SND_SOC_TEGRA186_ASRC_WAR
|
|
regmap_read(arad->regmap, ARAD_LANE_REG(
|
|
TEGRA186_ARAD_LANE1_RATIO_INTEGER_PART,
|
|
i), &inte);
|
|
regmap_read(arad->regmap, ARAD_LANE_REG(
|
|
TEGRA186_ARAD_LANE1_RATIO_FRACTIONAL_PART,
|
|
i), &frac);
|
|
|
|
/* source SW:1 and ARAD:0 */
|
|
tegra186_asrc_set_source(i, 1);
|
|
tegra186_update_asrc_ratio(i, inte, frac);
|
|
tegra186_asrc_set_source(i, 0);
|
|
tegra186_asrc_event(i, STREAM_ENABLE, 1);
|
|
#endif
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&arad->int_lock, flags);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
#endif
|
|
|
|
static int tegra186_arad_platform_probe(struct platform_device *pdev)
|
|
{
|
|
struct tegra186_arad *arad;
|
|
struct resource *mem, *memregion;
|
|
void __iomem *regs;
|
|
int ret = 0;
|
|
const struct of_device_id *match;
|
|
struct tegra186_arad_soc_data *soc_data;
|
|
|
|
match = of_match_device(tegra186_arad_of_match, &pdev->dev);
|
|
if (!match) {
|
|
dev_err(&pdev->dev, "Error: No device match found\n");
|
|
ret = -ENODEV;
|
|
goto err;
|
|
}
|
|
soc_data = (struct tegra186_arad_soc_data *)match->data;
|
|
|
|
arad = devm_kzalloc(&pdev->dev,
|
|
sizeof(struct tegra186_arad), GFP_KERNEL);
|
|
if (!arad) {
|
|
dev_err(&pdev->dev, "Can't allocate tegra210_arad\n");
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
dev_set_drvdata(&pdev->dev, arad);
|
|
|
|
arad->soc_data = soc_data;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!mem) {
|
|
dev_err(&pdev->dev, "No memory resource\n");
|
|
ret = -ENODEV;
|
|
goto err;
|
|
}
|
|
|
|
memregion = devm_request_mem_region(&pdev->dev, mem->start,
|
|
resource_size(mem), DRV_NAME);
|
|
if (!memregion) {
|
|
dev_err(&pdev->dev, "Memory region already claimed\n");
|
|
ret = -EBUSY;
|
|
goto err;
|
|
}
|
|
|
|
regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
|
|
if (!regs) {
|
|
dev_err(&pdev->dev, "ioremap failed\n");
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
arad->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
|
|
&tegra186_arad_regmap_config);
|
|
if (IS_ERR(arad->regmap)) {
|
|
dev_err(&pdev->dev, "regmap init failed\n");
|
|
ret = PTR_ERR(arad->regmap);
|
|
goto err;
|
|
}
|
|
regcache_cache_only(arad->regmap, true);
|
|
|
|
if (of_property_read_u32(pdev->dev.of_node,
|
|
"nvidia,ahub-arad-id",
|
|
&pdev->dev.id) < 0) {
|
|
dev_err(&pdev->dev,
|
|
"Missing property nvidia,ahub-arad-id\n");
|
|
ret = -ENODEV;
|
|
goto err;
|
|
}
|
|
tegra186_arad_runtime_resume(&pdev->dev);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
ret = snd_soc_register_codec(&pdev->dev, &tegra186_arad_codec,
|
|
tegra186_arad_dais,
|
|
ARRAY_SIZE(tegra186_arad_dais));
|
|
if (ret != 0) {
|
|
dev_err(&pdev->dev, "Could not register CODEC: %d\n", ret);
|
|
goto err_suspend;
|
|
}
|
|
|
|
#ifdef CONFIG_SND_SOC_TEGRA186_ARAD_WAR
|
|
arad->irq = platform_get_irq(pdev, 0);
|
|
ret = devm_request_irq(&pdev->dev,
|
|
tegra_agic_irq_get_virq(arad->irq),
|
|
tegra186_arad_interrupt_handler,
|
|
0, pdev->name, &pdev->dev);
|
|
if (ret)
|
|
dev_err(&pdev->dev, "Could not register ARAD INTERRUPT\n");
|
|
spin_lock_init(&arad->int_lock);
|
|
#endif
|
|
return 0;
|
|
|
|
err_suspend:
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra186_arad_runtime_suspend(&pdev->dev);
|
|
err_pm_disable:
|
|
pm_runtime_disable(&pdev->dev);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static int tegra186_arad_platform_remove(struct platform_device *pdev)
|
|
{
|
|
snd_soc_unregister_codec(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra186_arad_runtime_suspend(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra186_arad_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra186_arad_runtime_suspend,
|
|
tegra186_arad_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra186_arad_suspend, NULL)
|
|
};
|
|
|
|
static struct platform_driver tegra186_arad_driver = {
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = tegra186_arad_of_match,
|
|
.pm = &tegra186_arad_pm_ops,
|
|
},
|
|
.probe = tegra186_arad_platform_probe,
|
|
.remove = tegra186_arad_platform_remove,
|
|
};
|
|
module_platform_driver(tegra186_arad_driver)
|
|
|
|
MODULE_AUTHOR("Junghyun Kim <juskim@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra186 ARAD ASoC driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
MODULE_DEVICE_TABLE(of, tegra186_arad_of_match);
|