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39e4507117
Tegra210 and later audio drivers have been using 'tegra-alt' directory from the beginning. As per the upstream roadmap, we plan to use the same 'tegra' directory and place all the drivers under it. This patch thus moves all the drivers to 'tegra' and renames the files accordingly. The '_alt' suffix is removed from header and source files. For some files still the '_alt' suffix is retained because 'tegra' already has the corresponding files. Manual merge of following files is needed and will be done in separate commits. * tegra_asoc_utils_alt.c and tegra_asoc_utils.c * tegra_asoc_utils_alt.h and tegra_asoc_utils.h * tegra_pcm_alt.c and tegra_pcm.c * tegra_pcm_alt.h and tegra_pcm.h * Corresponding Makefile and Kconfig files. * Source files related to ADSP audio, FPGA, bandwidth manager are not considered at the moment and will be tracked separately. Bug 2845498 Change-Id: I51dae3971c72b58d921dc19f0553a83422fd3f9e Signed-off-by: Sameer Pujar <spujar@nvidia.com>
145 lines
6.1 KiB
C
145 lines
6.1 KiB
C
/*
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* tegra210_mvc_alt.h - Definitions for Tegra210 MVC driver
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*
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* Copyright (c) 2014-2019 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA210_MVC_ALT_H__
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#define __TEGRA210_MVC_ALT_H__
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/*
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* MVC_AXBAR_RX registers are with respect to AXBAR.
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* The data is coming from AXBAR to MVC for playback.
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*/
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#define TEGRA210_MVC_AXBAR_RX_STATUS 0x0c
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#define TEGRA210_MVC_AXBAR_RX_INT_STATUS 0x10
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#define TEGRA210_MVC_AXBAR_RX_INT_MASK 0x14
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#define TEGRA210_MVC_AXBAR_RX_INT_SET 0x18
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#define TEGRA210_MVC_AXBAR_RX_INT_CLEAR 0x1c
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#define TEGRA210_MVC_AXBAR_RX_CIF_CTRL 0x20
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#define TEGRA210_MVC_AXBAR_RX_CYA 0x24
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#define TEGRA210_MVC_AXBAR_RX_DBG 0x28
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/*
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* MVC_AXBAR_TX registers are with respect to AXBAR.
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* The data is going out of MVC for playback.
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*/
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#define TEGRA210_MVC_AXBAR_TX_STATUS 0x4c
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#define TEGRA210_MVC_AXBAR_TX_INT_STATUS 0x50
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#define TEGRA210_MVC_AXBAR_TX_INT_MASK 0x54
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#define TEGRA210_MVC_AXBAR_TX_INT_SET 0x58
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#define TEGRA210_MVC_AXBAR_TX_INT_CLEAR 0x5c
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#define TEGRA210_MVC_AXBAR_TX_CIF_CTRL 0x60
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#define TEGRA210_MVC_AXBAR_TX_CYA 0x64
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#define TEGRA210_MVC_AXBAR_TX_DBG 0x68
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/* Register offsets from TEGRA210_MVC*_BASE */
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#define TEGRA210_MVC_ENABLE 0x80
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#define TEGRA210_MVC_SOFT_RESET 0x84
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#define TEGRA210_MVC_CG 0x88
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#define TEGRA210_MVC_STATUS 0x90
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#define TEGRA210_MVC_INT_STATUS 0x94
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#define TEGRA210_MVC_CTRL 0xa8
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#define TEGRA210_MVC_SWITCH 0xac
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#define TEGRA210_MVC_INIT_VOL 0xb0
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#define TEGRA210_MVC_TARGET_VOL 0xd0
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#define TEGRA210_MVC_DURATION 0xf0
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#define TEGRA210_MVC_DURATION_INV 0xf4
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#define TEGRA210_MVC_POLY_N1 0xf8
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#define TEGRA210_MVC_POLY_N2 0xfc
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#define TEGRA210_MVC_PEAK_CTRL 0x100
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL 0x104
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_DATA 0x108
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#define TEGRA210_MVC_PEAK_VALUE 0x10c
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#define TEGRA210_MVC_CONFIG_ERR_TYPE 0x12c
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#define TEGRA210_MVC_CYA 0x130
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#define TEGRA210_MVC_DBG 0x138
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/* Fields in TEGRA210_MVC_ENABLE */
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#define TEGRA210_MVC_EN_SHIFT 0
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#define TEGRA210_MVC_EN (1 << TEGRA210_MVC_EN_SHIFT)
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#define TEGRA210_MVC_MUTE_SHIFT 8
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#define TEGRA210_MVC_MUTE_MASK (0xff << TEGRA210_MVC_MUTE_SHIFT)
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#define TEGRA210_MVC_MUTE_EN (0xff << TEGRA210_MVC_MUTE_SHIFT)
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#define TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT 30
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#define TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK (1 << TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT)
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#define TEGRA210_MVC_PER_CHAN_CTRL_EN (1 << TEGRA210_MVC_PER_CHAN_CTRL_EN_SHIFT)
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#define TEGRA210_MVC_CURVE_TYPE_SHIFT 1
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#define TEGRA210_MVC_CURVE_TYPE_MASK \
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(1 << TEGRA210_MVC_CURVE_TYPE_SHIFT)
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#define TEGRA210_MVC_CURVE_TYPE_POLY \
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(0 << TEGRA210_MVC_CURVE_TYPE_SHIFT)
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#define TEGRA210_MVC_CURVE_TYPE_LINEAR \
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(1 << TEGRA210_MVC_CURVE_TYPE_SHIFT)
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#define TEGRA210_MVC_VOLUME_SWITCH_SHIFT 2
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#define TEGRA210_MVC_VOLUME_SWITCH_MASK (1 << TEGRA210_MVC_VOLUME_SWITCH_SHIFT)
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#define TEGRA210_MVC_VOLUME_SWITCH_TRIGGER (1 << TEGRA210_MVC_VOLUME_SWITCH_SHIFT)
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#define TEGRA210_MVC_COEFF_SWITCH_SHIFT 1
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#define TEGRA210_MVC_COEFF_SWITCH_MASK (1 << TEGRA210_MVC_COEFF_SWITCH_SHIFT)
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#define TEGRA210_MVC_COEFF_SWITCH_TRIGGER (1 << TEGRA210_MVC_COEFF_SWITCH_SHIFT)
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#define TEGRA210_MVC_DURATION_SWITCH_SHIFT 0
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#define TEGRA210_MVC_DURATION_SWITCH_MASK (1 << TEGRA210_MVC_DURATION_SWITCH_SHIFT)
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#define TEGRA210_MVC_DURATION_SWITCH_TRIGGER (1 << TEGRA210_MVC_DURATION_SWITCH_SHIFT)
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#define TEGRA210_MVC_INIT_VOL_DEFAULT_POLY 0x01000000
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#define TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR 0x00000000
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/* Fields in TEGRA210_MVC ram ctrl */
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_READ_BUSY_SHIFT 31
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_READ_BUSY_MASK (1 << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_READ_BUSY_SHIFT)
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_READ_BUSY (1 << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_READ_BUSY_SHIFT)
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_SEQ_READ_COUNT_SHIFT 16
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_SEQ_READ_COUNT_MASK (0xff << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_SEQ_READ_COUNT_SHIFT)
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RW_SHIFT 14
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RW_MASK (1 << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RW_SHIFT)
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RW_WRITE (1 << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RW_SHIFT)
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_ADDR_INIT_EN_MASK (1 << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_SEQ_ACCESS_EN_MASK (1 << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RAM_ADDR_SHIFT 0
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#define TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RAM_ADDR_MASK (0x1ff << TEGRA210_MVC_AHUBRAMCTL_CONFIG_RAM_CTRL_RAM_ADDR_SHIFT)
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enum {
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CURVE_POLY,
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CURVE_LINEAR,
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};
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struct tegra210_mvc {
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struct regmap *regmap;
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int poly_coeff[9];
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int poly_n1, poly_n2, duration, duration_inv;
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int volume;
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unsigned int curve_type;
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unsigned int cif_channels;
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unsigned int audio_bits;
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unsigned int format_in;
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};
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#endif
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