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ab3d2a477f
Adding a module that disables cg on t264 specifically. This is meant for purely internal usage by the SSG and noise-characterization teams. We are making use of some override signals that remain on a per-core basis for this purpose. Bug 4697511 Change-Id: I04093b97b10e1a87bfaa2615573b284a6f1ef4f3 Signed-off-by: Ishan Shah <ishah@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3237175 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
138 lines
3.1 KiB
C
138 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved.
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*
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* Module to disable Clock-Gating on WFI for T264.
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*
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <linux/irqdesc.h>
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#include <linux/interrupt.h>
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#include <linux/debugfs.h>
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#include <linux/cpu.h>
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#include <linux/cpuidle.h>
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#define CCPLEX_SOCKET0_MMI0_BASE 0x8130000000
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#define CCPLEX_SOCKET0_MMIO_SIZE 0x3fffff
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/* Two cores to a cluster */
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#define T264_CORE_OFFSET(cl) ((cl % 2) * 0x8)
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/* Two clusters to a switch */
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#define T264_CLUSTER_OFFSET(cl) (((cl % 4) / 2) * 0x1000)
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/* Four switches in the system */
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#define T264_SWITCH_OFFSET(cl) ((cl / 4) * 0x100000)
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/* Determine the per-core CG Disable Register */
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/* coreN_archcg_clken */
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#define T264_CG_DISABLE_REG(base, cl) \
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(base + T264_SWITCH_OFFSET(cl) + T264_CLUSTER_OFFSET(cl) \
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+ T264_CORE_OFFSET(cl) + 0x218)
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static void __iomem *ccplex_mmio_base;
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static void __iomem *get_t264_cg_disable_reg(void __iomem *base, int core)
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{
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return T264_CG_DISABLE_REG(base, core);
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}
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static int cg_disable_write(void *data, u64 val)
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{
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void __iomem *reg = (void __iomem *) data;
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if (val == 0) {
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writel(0x00, reg);
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} else {
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writel(0x3, reg);
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}
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return 0;
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}
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static int cg_disable_read(void *data, u64 *val)
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{
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void __iomem *reg = (void __iomem *) data;
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u64 regval;
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regval = readl(reg);
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if (regval == 0) {
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*val = 0;
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} else {
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*val = 1;
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}
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(idle_state_fops, cg_disable_read, cg_disable_write, "%llu\n");
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static struct dentry *cpuidle_cg_disable_node;
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static int init_debugfs(void)
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{
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int cpu;
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cpuidle_cg_disable_node = debugfs_create_dir("cpuidle_cg_disable", NULL);
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if (!cpuidle_cg_disable_node)
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goto err_out;
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for_each_possible_cpu(cpu) {
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/* Size = 7 = cpu (3) + %d (3 from max 1000 cores) + \n (1) */
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char str_buf[7];
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struct dentry *debugfs_dir;
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snprintf(str_buf, 7, "cpu%d", cpu);
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debugfs_dir = debugfs_create_dir(str_buf, cpuidle_cg_disable_node);
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if (!debugfs_dir) {
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goto err_out;
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}
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debugfs_create_file("disable_cg", 0600,
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debugfs_dir, (void *) get_t264_cg_disable_reg(ccplex_mmio_base, cpu),
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&idle_state_fops);
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}
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return 0;
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err_out:
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pr_err("%s: Couldn't create debugfs node for cpuidle\n", __func__);
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debugfs_remove_recursive(cpuidle_cg_disable_node);
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return -ENOMEM;
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}
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static int __init cpuidle_cg_disable_probe(void)
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{
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int error;
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/* Set up the IO Mapping */
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ccplex_mmio_base = ioremap(CCPLEX_SOCKET0_MMI0_BASE, CCPLEX_SOCKET0_MMIO_SIZE);
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if (IS_ERR(ccplex_mmio_base)) {
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error = PTR_ERR(ccplex_mmio_base);
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goto mapping_err_out;
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}
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error = init_debugfs();
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if (error) {
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goto debugfs_err_out;
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}
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return 0;
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mapping_err_out:
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pr_err("%s: Couldn't map the CPU's mmcrab registers\n", __func__);
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debugfs_err_out:
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return error;
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}
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static void __exit cpuidle_cg_disable_remove(void)
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{
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debugfs_remove_recursive(cpuidle_cg_disable_node);
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iounmap(ccplex_mmio_base);
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}
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module_init(cpuidle_cg_disable_probe);
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module_exit(cpuidle_cg_disable_remove);
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MODULE_AUTHOR("Ishan Shah <ishah@nvidia.com>");
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MODULE_DESCRIPTION("clock gating disable driver");
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MODULE_LICENSE("GPL");
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