mirror of
git://nv-tegra.nvidia.com/linux-nv-oot.git
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054f2a1a22
The dt node that includes ivc properties and the dev does not have to be same node. GPU could be PCIE endpoint device which does not have corresponding dt node, so GPU driver uses PCIE controller node to store ivc properties. Jira GVSCI-15779 Change-Id: Ibf9c8f17eac1accceee5fe8d5eca3521cda934b9 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2884313 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Austin Tajiri <atajiri@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
30 lines
978 B
C
30 lines
978 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2013-2023, NVIDIA Corporation. All rights reserved.
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*
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* Tegra Graphics Virtualization Communication Framework
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*/
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#ifndef __TEGRA_GR_COMM_H
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#define __TEGRA_GR_COMM_H
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#include <linux/device.h>
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#define TEGRA_GR_COMM_ID_SELF (0xFF)
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int tegra_gr_comm_init(struct device *dev, struct device_node *dn, u32 elems,
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const size_t *queue_sizes, u32 queue_start, u32 num_queues);
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void tegra_gr_comm_deinit(u32 queue_start, u32 num_queues);
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int tegra_gr_comm_send(u32 peer, u32 index, void *data,
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size_t size);
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int tegra_gr_comm_recv(u32 index, void **handle, void **data,
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size_t *size, u32 *sender);
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int tegra_gr_comm_sendrecv(u32 peer, u32 index, void **handle,
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void **data, size_t *size);
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void tegra_gr_comm_release(void *handle);
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u32 tegra_gr_comm_get_server_vmid(void);
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void *tegra_gr_comm_oob_get_ptr(u32 peer, u32 index,
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void **ptr, size_t *size);
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void tegra_gr_comm_oob_put_ptr(void *handle);
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#endif
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