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92ac7bc35a
Port camera drivers below from /kenrel/nvidia to /kernel/nvidia-oot as OOT modules: - Fusa-capture driver - Tegra V4L2 framework driver - vi/csi driver - tegra camera platform driver Change-Id: I390af27096425bb11e0934201dd1a90f001bb3fa Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2780698 Reviewed-by: FNU Raunak <fraunak@nvidia.com> Reviewed-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-by: Shiva Dubey <sdubey@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
72 lines
2.1 KiB
C
72 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Tegra NVCSI Driver
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*
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* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __UAPI_LINUX_NVHOST_NVCSI_IOCTL_H
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#define __UAPI_LINUX_NVHOST_NVCSI_IOCTL_H
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#if !defined(__KERNEL__)
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#define __user
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#endif
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/* Bitmap
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*
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* | PHY_2 | PHY_1 | PHY_0 |
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* | 11 10 | 9 8 | 7 6 | 5 4 | 3 2 | 1 0 |
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* | CILB | CILA | CILB | CILA | CILB | CILA |
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*/
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#define PHY_0_CIL_A_IO0 0
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#define PHY_0_CIL_A_IO1 1
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#define PHY_0_CIL_B_IO0 2
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#define PHY_0_CIL_B_IO1 3
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#define PHY_1_CIL_A_IO0 4
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#define PHY_1_CIL_A_IO1 5
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#define PHY_1_CIL_B_IO0 6
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#define PHY_1_CIL_B_IO1 7
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#define PHY_2_CIL_A_IO0 8
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#define PHY_2_CIL_A_IO1 9
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#define PHY_2_CIL_B_IO0 10
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#define PHY_2_CIL_B_IO1 11
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#define PHY_3_CIL_A_IO0 12
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#define PHY_3_CIL_A_IO1 13
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#define PHY_3_CIL_B_IO0 14
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#define PHY_3_CIL_B_IO1 15
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#define NVCSI_PHY_CIL_NUM_LANE 16
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#define NVCSI_PHY_0_NVCSI_CIL_A_IO0 (0x1 << PHY_0_CIL_A_IO0)
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#define NVCSI_PHY_0_NVCSI_CIL_A_IO1 (0x1 << PHY_0_CIL_A_IO1)
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#define NVCSI_PHY_0_NVCSI_CIL_B_IO0 (0x1 << PHY_0_CIL_B_IO0)
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#define NVCSI_PHY_0_NVCSI_CIL_B_IO1 (0x1 << PHY_0_CIL_B_IO1)
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#define NVCSI_PHY_1_NVCSI_CIL_A_IO0 (0x1 << PHY_1_CIL_A_IO0)
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#define NVCSI_PHY_1_NVCSI_CIL_A_IO1 (0x1 << PHY_1_CIL_A_IO1)
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#define NVCSI_PHY_1_NVCSI_CIL_B_IO0 (0x1 << PHY_1_CIL_B_IO0)
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#define NVCSI_PHY_1_NVCSI_CIL_B_IO1 (0x1 << PHY_1_CIL_B_IO1)
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#define NVCSI_PHY_2_NVCSI_CIL_A_IO0 (0x1 << PHY_2_CIL_A_IO0)
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#define NVCSI_PHY_2_NVCSI_CIL_A_IO1 (0x1 << PHY_2_CIL_A_IO1)
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#define NVCSI_PHY_2_NVCSI_CIL_B_IO0 (0x1 << PHY_2_CIL_B_IO0)
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#define NVCSI_PHY_2_NVCSI_CIL_B_IO1 (0x1 << PHY_2_CIL_B_IO1)
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#define NVCSI_PHY_3_NVCSI_CIL_A_IO0 (0x1 << PHY_3_CIL_A_IO0)
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#define NVCSI_PHY_3_NVCSI_CIL_A_IO1 (0x1 << PHY_3_CIL_A_IO1)
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#define NVCSI_PHY_3_NVCSI_CIL_B_IO0 (0x1 << PHY_3_CIL_B_IO0)
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#define NVCSI_PHY_3_NVCSI_CIL_B_IO1 (0x1 << PHY_3_CIL_B_IO1)
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#define NVCSI_PHY_NUM_BRICKS 4
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#define NVHOST_NVCSI_IOCTL_MAGIC 'N'
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#define NVHOST_NVCSI_IOCTL_DESKEW_SETUP _IOW(NVHOST_NVCSI_IOCTL_MAGIC, 1, long)
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#define NVHOST_NVCSI_IOCTL_DESKEW_APPLY _IOW(NVHOST_NVCSI_IOCTL_MAGIC, 2, long)
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#endif
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